Xilinx LUT behavior question

If I change one input to a LUT, and leave the other three inputs unchanged,
such that both the original and new output will be the same (e.g., both '1'),
can there be a glitch in the output?

Good question, often asked:
No glitch, and that behavior is guaranteed by the decoding structure.

Further, if you change two pins, and you know that the output is
identical for all 4 permutations of these 2 bits, there also is no
glitch.
And you can stretch that to 3 pins, where all 8 permutations must give
identical results to avoid a glitch, although this last one may be an
unrealisticl situation.

I have answered this particular question many times over the past 15
years.
Peter Alfke, Xilinx Applications

"Eric Smith" <eric@brouhaha.com> wrote in message 
news:qhacflpr6b.fsf@ruckus.brouhaha.com...
> If I change one input to a LUT, and leave the other three inputs 
> unchanged,
> such that both the original and new output will be the same (e.g., both 
> '1'),
> can there be a glitch in the output?

Hi Eric,
You got a good answer from Peter. However, my smarty pants response is to 
never put yourself in a position where you care what the answer is! You'd 
never clock a FF from the output of a LUT. Would you? ;-)
Cheers, Syms. 

Hi All,

Very helpful discussion going on atleast for me.
Recently I had faced one problem.
I was implementing a module/Entity which is intended to be used in
cascaded configurations for parallel operations. (The Number of cascade
Instances are limited by clock period and pipeline architecture).
As it has a pipeline architecture some signals(inter_instance signals)
are driven by a registered stage output for first instance and are
actually combi outputs driving another combi block in the other
instance and thus the pipeline works. Hope My explanation is clear...?

so naturaly in the first instance which will be driving the chain of
cascade instances will have both select and data lines of a mux or LUT
driven by a registered stage.
Here most probability is there of getting a glitch generated, which
will propogate to the last instance and may create a problem where the
final o/p is going to get registered in the last instance of cascade
chain.
I tried many was of implementing this combi structure in Altera Stratix
but glitch is still there.

Any guideline or suggetions will be greatly helpful...

Thanks & Regards
Kedar

kedarpapte@gmail.com wrote:

> I tried many was of implementing this combi structure in Altera Stratix
> but glitch is still there.
> Any guideline or suggetions will be greatly helpful...

I would suggest eliminating glitches using synchronous
design techniques and verifying Fmax using Quartus static timing.

         -- Mike Treseler

I asked about the possibility of LUT output glitches, and
Peter Alfke replied:
> Good question, often asked:
> No glitch, and that behavior is guaranteed by the decoding structure.
[...]
> I have answered this particular question many times over the past 15
> years.

Sorry to bring it up for the umpteenth time, then, but thanks for the
answer.

Should I have been able to figure this out from the data sheet or other
documentation?  The description of the Function Generator on page 12
of DS099-2 v1.4 (Spartan 3 functional description) didn't make it clear
to me that I could count on a LUT being glitchless.

Are the FxMUX multiplexers similarly designed for glitchless transitions?

(For those that aren't aware of it, some simple 2:1 mux designs are
suceptible to glitches when switching between inputs that are the same
state.  For instance, if you use two AND gates, an inverter, and an OR,
you can have a glitch to 0 when switching between two inputs that are 1.
If a CMOS mux is implemented with two transmission gates, this shouldn't
occur unless output loading affects the output state while both TGs are
open.)

Eric

I asked about the possibility of glitches on LUT outputs.  Peter gave
a definitive response, and Symon wrote:
> You got a good answer from Peter. However, my smarty pants response is to 
> never put yourself in a position where you care what the answer is! You'd 
> never clock a FF from the output of a LUT. Would you? ;-)

I fully agree; my designs are fully synchronous.

The reason the whole question came up is that a friend is trying to
cram old TTL logic designs into an FPGA without redesigning them to
be synchronous, so he has latches, S-R flops, and other horrible stuff.
I was wondering whether an S-R flop implemented as two cross-coupled
gates using a LUT for each gate could even be guaranteed to function
correctly; if LUTs can have output glitches they would not.

I'm still trying to convince my friend that his approach is likely to
cause him much grief.

Eric

Eric,

Some comments on glitches:

Because the LUT is really more than one stage of multiplexing, the last 
stage has the fastest response, with the least glitching (or none at 
all, depending on how such mux'ing is actually accomplished, ie pass 
gate mux, or logic mux).

The FMUX is similar, in that the last stage will always result in the 
least possibility of changes occuring leading to intermediate states.

Last stage is a relative term, as last is what you make it by how you 
use it.  If you never change an input on the real last stage, the 'last 
stage' becomes the previous one with an input that selects.

Earlier product families treated all LUT input delays equal, as the 
routing couldn't really take advantage of using the more detailed 
information.  I believe now in FPGA Editor for V4 you see the different 
delays on each input.

With more advancements in software, one can use the individual delays to 
advantage and get better performance, and also less glitch power (power 
aware routing).

Getting all the delays to all stages of mux in the LUT from the previous 
stages of logic is a nightmare only suitable for a computer to crunch 
on.  How valid it will be over all process/voltage/temperature is 
another practical matter.  Claiming "glitch free" for all corners is 
something I don't feel comfortable with (as I don't control the inputs 
nor their possible timing), but claiming minimal glitching is OK (or no 
glitches while transitioning when input delays are fixed and known). 
Especially when in a synchronous system, the only penalty of glitches is 
slightly more power as lines get charged/discharged/charged....

Now how much less power, and how much better performance is something 
that is often claimed (and disputed) so I won't go into that except to 
say there is some possibility here for improvements.

Those that have hand routed designs to squeeze the most performance (or 
least glitching power loss) seem to feel that this is worth it. 
Theoretically it also seems to be valid.

Austin


Eric Smith wrote:

> I asked about the possibility of LUT output glitches, and
> Peter Alfke replied:
> 
>>Good question, often asked:
>>No glitch, and that behavior is guaranteed by the decoding structure.
> 
> [...]
> 
>>I have answered this particular question many times over the past 15
>>years.
> 
> 
> Sorry to bring it up for the umpteenth time, then, but thanks for the
> answer.
> 
> Should I have been able to figure this out from the data sheet or other
> documentation?  The description of the Function Generator on page 12
> of DS099-2 v1.4 (Spartan 3 functional description) didn't make it clear
> to me that I could count on a LUT being glitchless.
> 
> Are the FxMUX multiplexers similarly designed for glitchless transitions?
> 
> (For those that aren't aware of it, some simple 2:1 mux designs are
> suceptible to glitches when switching between inputs that are the same
> state.  For instance, if you use two AND gates, an inverter, and an OR,
> you can have a glitch to 0 when switching between two inputs that are 1.
> If a CMOS mux is implemented with two transmission gates, this shouldn't
> occur unless output loading affects the output state while both TGs are
> open.)
> 
> Eric

Your friend's TTL designs must be really old. As early as 1969 (when I
was at Fairchild Applications) we touted synchronous design with 4-bit
synchronous counter/registers (the 9310 and 9316, copied by T.I. and
called the 74160 and 74161) and other register-oriented logic.
Enlightened circles frowned upon making latches out of gates, as early
as 1968.

BTW, you can build a latch out of one single LUT, by feeding its output
back to its input. Then you have 3 control inputs, and you can make
them be anything you wish, D, S, R, Enable and even clock...
Things for a lazy afternoon, not for serious business...
Peter Alfke

Just to get back to the original question (which was kind of academic):
my answer still stands. The muxing inside the LUT is done by pass
transistors, and the internal capacitance holds the value during
non-overlapped switching. So: no glitches.
Austin describes glitching in a more general sense, and then mentions
on the delay differences of different LUT address inputs. Good info,
but does not contradict my statement.
Peter Alfke