xilinx constraint

Hello all,

Environment details
FPGA      : Xilinx spartan 3(xc3s200-vq100) speed grade 4
ISE          : version 7.1.04i
Modelsim : verion ModelSim XE III/Starter 6.0a

I am Monica from Germany.I am pretty new to FPGA development.Now I am
developing a small interface module which generates MPEG 2 stream.

I drive mpegSync and mpegData at the same time(same location in VHDL)
but however in Place And Route simulation I am observing that mpegData
is lagging mpegSync by 7ns.I want both the mpegSync and mpegData to be
asserted at the same time.

Behaviuoral simulation is fine but PAR simulation is not fine may be
because mpegData is routed with longer nets before it reaches I/O pad.

Can anybody give me a hint how to drive them nearly the same time?Is
there any xilinx constraint i can use?

Thanks a lot in advance.
Monica DSouza,
Germany

Hi Monica,

Can you place those registers in IOBs? This will give
you equal (and faster, if that is ok) clock to output times.

Use ISE Help within Project Navigator to show you how to do that.

Alan

Dear Mr.Alan,

Thank you very much for your suggestion.But unfortunately,mpegData is
not a register,it is only a wire from Block RAM(signal).Where as
mpegSync is a register.

Is there any other alternative?

thank you,
Monica

Hi Monica,

Could you pipeline the mpegData and mpegSync signals
with registers before outputing them? Then you could put
the pipeline registers in the IOBs?

Alan

Hi Monica,

Could you pipeline the mpegData and mpegSync signals
with registers before outputing them? Then you could put
the pipeline registers in the IOBs?

Alan

Dear Mr.Alan,

I have changed my logic such mpegData is considered as a register
instead of combitional logic and kept them in IOBs(through help).The
output is not only good but also fast.Thanks a lot for your suggestion.

Can you please tell me what is the idea behind keeping these registers
in IOBs?What are these IOBs?

Thank you very much for your help.
Monica DSouza,
Germany

Hi Monica,

An IOB is an area of logic next to the input/output pad,
as opposed to part of the core logic.

Constraining the tool to place the register in the IOB thus
gives you better clock-to-output times, as the flip-flop is
placed next to the output buffer/pad.

Glad to have been able to help.

Alan

Monica wrote:

> Dear Mr.Alan,
> 
> I have changed my logic such mpegData is considered as a register
> instead of combitional logic and kept them in IOBs(through help).The
> output is not only good but also fast.Thanks a lot for your suggestion.
> 
> Can you please tell me what is the idea behind keeping these registers
> in IOBs?What are these IOBs?
> 
> Thank you very much for your help.
> Monica DSouza,
> Germany
> 

Monica,

The idea is to normalize the delay from the pin to the first register in 
the design.  Using the flip-flop in the IOB (Input-Output Block) uses 
only the dedicated routing wire between the device pin and the input or 
output flip-flop, so the variability due to different routing solutions 
is removed.

Using the IOB registers is also prudent because it isolates the timing 
inside the FPGA from the timing at the board level, which eliminates 
problems down the road when you make incremental improvements to the 
design.  Using these registers also tends to make a successful place and 
route less dependent on the pin assignments.

Monica wrote:

>Dear Mr.Alan,
>
>I have changed my logic such mpegData is considered as a register
>instead of combitional logic and kept them in IOBs(through help).The
>output is not only good but also fast.Thanks a lot for your suggestion.
>  
>
Ah, well, that explains the 7 ns lag.  While mpegSync is prompt from the FF
(register) the combinatorial logic on mpegData following the last 
register produced the
delay.

Jon

Hello all,

Thank you very much for explaining me everything clearly.The
suggestions and information is highly useful.I think I must more
homework to understand such problems.

Thanks alot,
Monica