Hi, I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is designed for the spartan 3 starter kit. It is just two ISSI IS61LV5128AL sram chips. I have tried writing a controller but cant seem to get it to work!! Thank a lot, Alastair
Digilent SRAM Controller
Started by ●December 15, 2005
Reply by ●December 15, 20052005-12-15
"al99999" <alastairlynch@gmail.com> schrieb im Newsbeitrag news:1134651034.610713.142150@f14g2000cwb.googlegroups.com...> Hi, > > I was wondering if anybody had designed a vhdl sram controller for the > Digilent Memory Expansion board that is designed for the spartan 3 > starter kit. It is just two ISSI IS61LV5128AL sram chips. I have > tried writing a controller but cant seem to get it to work!! > > Thank a lot, > > Alastair >SRAM doesnt need an controller, just connect it to whatever you want, if you did it right and the hardware is ok it will work. for EDK just add an EMC IP core to the SoC and setup the port connection in the ucf file, thats should be it. Antti
Reply by ●December 15, 20052005-12-15
Thanks, I'm not using EDK, only ISE, so I need a simple controller for the CE, OE and WE pins and to put the data and address on the correct buses at the right times.
Reply by ●December 15, 20052005-12-15
"al99999" <alastairlynch@gmail.com> schrieb im Newsbeitrag news:1134655074.184301.148800@g49g2000cwa.googlegroups.com...> Thanks, I'm not using EDK, only ISE, so I need a simple controller for > the CE, OE and WE pins and to put the data and address on the correct > buses at the right times. >that is just plain wires, if you have some circuitry that the SRAM can be connected. if you have trouble then just use VIO in chipscope, connected the SRAM to VIO pins and check the that the sram is really working properly, then go ahead and check your desing Antti
Reply by ●December 15, 20052005-12-15
Here is a RAM tester for the S3 kit: http://www.derepas.com/fabrice/hard/ It'll probably help you. Leon
Reply by ●December 15, 20052005-12-15
Thanks, trying to use VIO in chipscope with the code below and getting the following error: ERROR:Xst:2091 Different types for port <async_in> on entity and component for <vio>. Any ideas? Thanks entity vio_top is Port( control: in std_logic_vector(35 downto 0); async_in: in std_logic_vector(7 downto 0) ); end vio_top; architecture structure of vio_top is ------------------------------------------------------------------- -- -- VIO core component declaration -- ------------------------------------------------------------------- component vio port ( control : in std_logic_vector(35 downto 0); async_in : in std_logic_vector(7 downto 0) ); end component; begin ------------------------------------------------------------------- -- -- VIO core instance -- ------------------------------------------------------------------- i_vio : vio port map ( control => control, async_in => async_in ); end structure;
Reply by ●December 15, 20052005-12-15
al99999 wrote:> Thanks, I'm not using EDK, only ISE, so I need a simple controller for > the CE, OE and WE pins and to put the data and address on the correct > buses at the right times.fpga-cpu group threads about async SRAM strobe & OE timing: http://groups.yahoo.com/group/fpga-cpu/messages/539?threaded=1 http://groups.yahoo.com/group/fpga-cpu/messages/2039?threaded=1 fpga-cpu post with S3 kit SRAM tester: http://groups.yahoo.com/group/fpga-cpu/message/2177 The archive for that is here ftp://members.aol.com/fpgastuff/ram_test.zip And a post on re-compiling it under 7.1 : http://groups.google.com/group/comp.arch.fpga/msg/8955e7209e0c3929 That example includes pipelined SRAM control logic (registered address, data, and tristate contols in IOB registers, gated write pulse ) for the Xilinx/Digilent S3 eval kit. I've started a newer version of that, using a DCM duty cycle tweak, that works at around 60 Mhz with address & data lines all in SLOW slew rate mode, I'll probably update that archive file sometime next month. Brian