Inverter Chain Synthesis Problem

On 15 Dec 2005 19:35:22 -0800, "Davy" <zhushenli@gmail.com> wrote:

>Hi,
>
>  I work on Xilinx ISE, and my synthesis tool is XST and synplify.
>  I use verilog to write a Inverter Chain (delay ) like out =
>~(~(~(~...in)).
>  But the circuit be synthesised cancel all the invorter.
>
>  How to synthesis out all the inverter chain I want?
>
>Any suggestions will be appreciated!
>Best regards,
>Davy

There are some works about delay elements for asynchronous designs in
Xilinx FPGA. Google for them.