Verilog Program With A Problem

Hi to all,

I'm writing a program using verilog at the moment. The program that
i'm doing now is one of many blocks that will be finally linked up
together...Right now, i'm having some problems with my program...In my
program, i have a part where i need to compare the input(eingated) &
an output(eout_prev) of another program which is a D flip flop. So in
my program what should i define "eout_prev" as? An input, output, reg
...?
I need help urgently. Anyone can help me out ?

Thanks a lot! :-)

Below is my program & the D flip flop program ,and i have pointed to
where my problem lies.


--------------------------------------------------------------------------------

`timescale 1ns/1ps

module encoder(eingated, clr, clk, keydet, inhibit, eout);
 
input [3:0]eingated;
input clr, clk;
output keydet, inhibit;
output [3:0]eout;
reg [3:0]eout;
reg keydet, inhibit;

parameter idle = 1'b0, keypressed = 1'b1;
reg [1:0] cur_state, next_state;
reg eout_prev;


always @(posedge clk or negedge clr)
begin
      if(clr==0)
         cur_state = idle;
      else
         cur_state = next_state;
end



always@(cur_state or eingated or eout or eout_prev) 
begin
      case(cur_state)
      idle : if (eingated == 4'b1110 || eingated == 4'b1101 ||
eingated == 4'b1011 || eingated == 4'b0111)
             begin
                keydet = 1'b1;
                inhibit = 1'b1;
                next_state = keypressed;
             end
             else
             begin
                 keydet = 1'b0;
                 inhibit = 1'b0;
                 next_state = idle;
             end

     
  keypressed : if (eingated == 4'b1110 || eingated == 4'b1101 ||
eingated == 4'b1011 || eingated == 4'b0111)
               if (eout == eout_prev)       <------- What to define
               begin                                 "eout_prev" as?
                  keydet = 1'b1;		
                  inhibit = 1'b1;
                  next_state = keypressed;
               end
               else
               begin
                  keydet = 1'b0;		
                  inhibit = 1'b1;
                  next_state = idle;
               end
               else               
               begin
                  keydet = 1'b0;		
                  inhibit = 1'b0;
                  next_state = idle;
               end
      endcase
end


always @(eingated)
begin
   case (eingated)
       4'b1110: eout = 2'b00;
       4'b1101: eout = 2'b01;
       4'b1011: eout = 2'b10;  
       4'b0111: eout = 2'b11;
       default: eout = 2'b0;
   endcase    
end

endmodule      


--------------------------------------------------------------------------------
Below is the program of the D flip flop with output "eout_prev" :



`timescale 1ns/1ps

module eoutTemp(eout, keydet, clear, eout_prev);

input [1:0] eout;
input keydet, clear;

output [1:0] eout_prev;
reg [1:0] eout_prev;

always @(posedge keydet or negedge clear)
   if(clear==0)
      eout_prev<=2'b0;
   else eout_prev<={eout};

endmodule

In module encoder, "eout_prev" is an input

"Bose" <blueforest2@yahoo.com> &#1076;&#4294967295;&#4294967295;&#4294967295;&#4294967295;&#994;&#4294967295;&#4294967295;&#4294967295;&#4294967295;
:a395f2ee.0310252315.1ae0a344@posting.google.com...
> Hi to all,
>
> I'm writing a program using verilog at the moment. The program that
> i'm doing now is one of many blocks that will be finally linked up
> together...Right now, i'm having some problems with my program...In my
> program, i have a part where i need to compare the input(eingated) &
> an output(eout_prev) of another program which is a D flip flop. So in
> my program what should i define "eout_prev" as? An input, output, reg
> ...?
> I need help urgently. Anyone can help me out ?
>
> Thanks a lot! :-)
>
> Below is my program & the D flip flop program ,and i have pointed to
> where my problem lies.
>
>
> --------------------------------------------------------------------------
------
>
> `timescale 1ns/1ps
>
> module encoder(eingated, clr, clk, keydet, inhibit, eout);
>
> input [3:0]eingated;
> input clr, clk;
> output keydet, inhibit;
> output [3:0]eout;
> reg [3:0]eout;
> reg keydet, inhibit;
>
> parameter idle = 1'b0, keypressed = 1'b1;
> reg [1:0] cur_state, next_state;
> reg eout_prev;
>
>
> always @(posedge clk or negedge clr)
> begin
>       if(clr==0)
>          cur_state = idle;
>       else
>          cur_state = next_state;
> end
>
>
>
> always@(cur_state or eingated or eout or eout_prev)
> begin
>       case(cur_state)
>       idle : if (eingated == 4'b1110 || eingated == 4'b1101 ||
> eingated == 4'b1011 || eingated == 4'b0111)
>              begin
>                 keydet = 1'b1;
>                 inhibit = 1'b1;
>                 next_state = keypressed;
>              end
>              else
>              begin
>                  keydet = 1'b0;
>                  inhibit = 1'b0;
>                  next_state = idle;
>              end
>
>
>   keypressed : if (eingated == 4'b1110 || eingated == 4'b1101 ||
> eingated == 4'b1011 || eingated == 4'b0111)
>                if (eout == eout_prev)       <------- What to define
>                begin                                 "eout_prev" as?
>                   keydet = 1'b1;
>                   inhibit = 1'b1;
>                   next_state = keypressed;
>                end
>                else
>                begin
>                   keydet = 1'b0;
>                   inhibit = 1'b1;
>                   next_state = idle;
>                end
>                else
>                begin
>                   keydet = 1'b0;
>                   inhibit = 1'b0;
>                   next_state = idle;
>                end
>       endcase
> end
>
>
> always @(eingated)
> begin
>    case (eingated)
>        4'b1110: eout = 2'b00;
>        4'b1101: eout = 2'b01;
>        4'b1011: eout = 2'b10;
>        4'b0111: eout = 2'b11;
>        default: eout = 2'b0;
>    endcase
> end
>
> endmodule
>
>
> --------------------------------------------------------------------------
------
> Below is the program of the D flip flop with output "eout_prev" :
>
>
>
> `timescale 1ns/1ps
>
> module eoutTemp(eout, keydet, clear, eout_prev);
>
> input [1:0] eout;
> input keydet, clear;
>
> output [1:0] eout_prev;
> reg [1:0] eout_prev;
>
> always @(posedge keydet or negedge clear)
>    if(clear==0)
>       eout_prev<=2'b0;
>    else eout_prev<={eout};
>
> endmodule