Power Optimization: can the routing and placement really save power?

Recently posted on our website:

http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/resources/Virtex-4_Power_Case_Study.pdf

Is a case study in which the latest claims of power savings by the 
competitor's software are debunked.

I had intended to post this as part of the earlier thread, but I 
couldn't find the link to the above white paper.

If you ignore the superiority of Virtex 4, and just concentrate on the 
improvement in power from the tool, going from ~ 2.8 watts to ~ 2.6 
watts, or an improvement of 200 mW, is roughly an improvement of 7% less 
power.

So, routing and placement can really save some power.  Or perhaps, one 
should say poor routing and poor placement can increase power?

Or should one say that Virtex 4 uses so much less power, that talking 
about how much is 'saved' by the software tool is just a distraction to 
fool the unwary?

Austin

Energy consumption is rapidly eclipsing original product acquisition
cost when doing a total life-time cost analysis. For each Watt the IC
consumes, an additional 2-3 Watts are consumed in power conditioning,
conversion and cooling. 

Tom Seim

Another excellent reason why the lowest power device is preferable.

Austin

soar2morrow@yahoo.com wrote:

> Energy consumption is rapidly eclipsing original product acquisition
> cost when doing a total life-time cost analysis. For each Watt the IC
> consumes, an additional 2-3 Watts are consumed in power conditioning,
> conversion and cooling. 
> 
> Tom Seim
> 

Austin Lesea wrote:
> Recently posted on our website:
>
> http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/resources/Virtex-4_Power_Case_Study.pdf
>
> Is a case study in which the latest claims of power savings by the
> competitor's software are debunked.
>
> I had intended to post this as part of the earlier thread, but I
> couldn't find the link to the above white paper.
>
> If you ignore the superiority of Virtex 4, and just concentrate on the
> improvement in power from the tool, going from ~ 2.8 watts to ~ 2.6
> watts, or an improvement of 200 mW, is roughly an improvement of 7% less
> power.
>
> So, routing and placement can really save some power.  Or perhaps, one
> should say poor routing and poor placement can increase power?
>
> Or should one say that Virtex 4 uses so much less power, that talking
> about how much is 'saved' by the software tool is just a distraction to
> fool the unwary?
>
> Austin

It has long been known that appropriate placement and routing at the
physical layer can save power (not by a huge amount, but certainly of
the order of 5% or so depending on the circumstances). I've done a lot
of high speed design work, and minimising power is always an issue.

To find it can be done internally with the place and route tool is not
particularly surprising - indeed it is to be expected. I wonder when
the optimisation goal will be expanded to include 'power' (instead of
just speed and space).

Cheers

PeteS

> Recently posted on our website:
>
> http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/resources/Virtex-4_Power_Case_Study.pdf
>
> Is a case study in which the latest claims of power savings by the competitor's software are debunked.

Why are the power values measured at 25C and than scaled, in a way
that is not given in the paper, to 85C. Either provide the values
at 25C for reference or measure at 85C.

Another point: measurements are nice, but what about the worst case
values?

Martin 

"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> wrote in message 
news:43b3ef46$0$11094$3b214f66@tunews.univie.ac.at...
> Why are the power values measured at 25C and than scaled, in a way
> that is not given in the paper, to 85C.
Martin,
You did read this? "We collected power data at 25&#4294967295;C junction temperature 
from idle (0 MHz) up to 200 MHz, in 50Mhz steps. We then scaled the results 
to 85&#4294967295;C using static power data previously taken on Virtex-4 and Stratix II 
devices over temperature (see Xilinx White Paper WP223 for further 
information). Note that previous testing has shown that dynamic power does 
not vary significantly with temperature for either family of devices. "
Cheers, Syms. 

>> Why are the power values measured at 25C and than scaled, in a way
>> that is not given in the paper, to 85C.
> Martin,
> You did read this? "We collected power data at 25�C junction temperature from idle (0 MHz) up to 200 MHz, in 50Mhz steps. We then 
> scaled the results to 85�C using static power data previously taken on Virtex-4 and Stratix II devices over temperature (see 
> Xilinx White Paper WP223 for further information). Note that previous testing has shown that dynamic power does not vary 
> significantly with temperature for either family of devices. "
> Cheers, Syms.
I did read this and that is exactly the point I want to criticize.
I don't like measuring an aspect at one temperature point, not
showing the results, but scaling it 'in some way' to a different
temerature point for the final graph.

However, it's not so important - just a little bit of marketing
stuff ;-)

Martin 

Martin Schoeberl wrote:
> However, it's not so important - just a little bit of marketing
> stuff ;-)

No, Martin, it is not Marketing, it is Science.
Dynamic power and static power (leakage) have different temperature
dependencies:
Dynamic power is independent of temperature (since the frequency and
the capacitance do not change), while leakage current is very
temperature dependent.
The two can be added linearily.
Therefore it is not necessary to measure dynamic power at temperature.

And let this quibbling not obfuscate the basic fact:
Xilinx power consumption is much lower than Altera's.
We have to mention this because Altera makes so much noise about their
(non-existent) power superiority. Their claims are just Marketing BS...

Peter Alfke, Xilinx Applications

> Martin Schoeberl wrote:
>> However, it's not so important - just a little bit of marketing
>> stuff ;-)
>
> No, Martin, it is not Marketing, it is Science.

Let's say inbetween. The description of the method in
the Xilinx paper is not self contained. And the initial
criticism still holds: Where are the numbers at 25C?

About scientific relevant measurements: How many different
FPGAs (from different production runs) have been measured
for this paper?

> Dynamic power and static power (leakage) have different temperature
> dependencies:
> Dynamic power is independent of temperature (since the frequency and
> the capacitance do not change), while leakage current is very
> temperature dependent.
> The two can be added linearily.
> Therefore it is not necessary to measure dynamic power at temperature.

Ok, thanks for the clarification. But in this paper the
overall power was measured at 25C and the static power was
added from some other source for the 85C figure.

>
> And let this quibbling not obfuscate the basic fact:
> Xilinx power consumption is much lower than Altera's.

Didn't want to say that this is not correct, just a few
thoughts about methods in the Xilinx paper.

Martin

Martin Schoeberl wrote:
> > Ok, thanks for the clarification. But in this paper the
> overall power was measured at 25C and the static power was
> added from some other source for the 85C figure.
>
Martin, I find it hard to be patient with you.
If dynamic power is constant with temperature,
and static power increases monotonically with temperature,
and total power is always the linear sum of static and dynamic power,
then I can scientifically state that

Total Power @85 = static power @85 + dynamic power @25 degrees.

And that is not Marketing. (Which we all agree is almost a dirty word
in our circles).

Happy New Year !
Peter Alfke, Xilinx Applications