Clock generation

hi

I have a question: what is the proper way to generate c slow clock. I
have a spartan 3 development board with a 50 MHz external clock. What i
need is a 4MHz clock for an SPI interface. Since the DCM's can only
deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to
devide this clock some more. how is this done properly? a counter? Or
is ther any other sollution?

Thanks
Urban

>I have a question: what is the proper way to generate c slow clock. I
>have a spartan 3 development board with a 50 MHz external clock. What i
>need is a 4MHz clock for an SPI interface. Since the DCM's can only
>deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to
>devide this clock some more. how is this done properly? a counter? Or
>is ther any other sollution?

Is it really a clock?  Are you clocking FFs and state machines
with it?  If so, you need to worry about skew.

I'd expect it's just a signal named "clock" coming out of a FSM.
Or maybe that's just the way I'm thinking of it.

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Hi,

we all know how to count to 10 right?

I did think I can at least until I did see how
a binary counter works in Spartan3e - I am still confused:
the code in FPGA is at the end of the message,
it really is a very normal counter and should count

0,1,2,3,4,5,6,7... ?

well it doesnt, it counts

0,5,2,3,4,1,6,7... !

I have verified this behaviour multiply times and its still
counting this weird sequence where 1 and 5 are changed.

strange thing is that when I load the FPGA after loading the
counter design with another known good bitstream then the
second design works incorrectly about half of the outputs
are not toggling. This only happens when configuring with
non-impact tools. When the 2 designs are loaded with impact
then the second works properly. The weird counter works the
weird way no matter what tool is used to load the FPGA.

So as a real new year surprise I have now really seen an
FPGA that gets configured with partial/damaged bitstream
and still starts and reports done=1

Any suggestions what is wrong?
Is my counter RTL code wrong?

I have tested the wrong count both from my program and with
impact in JTAG debug mode, it really really counts wrong.

It can be that the FPGA is internally damaged as it
was almost the only IC that survived after on-board
switching supply got holes into the plastic and
Strataflash failed to respond to QRY (partially damaged
still responds to ID read).

hum when I have known fabric failing FPGA then its
really nice to work on FPGA test patterns to see
if they catch the failure

Antti


--------------- cut here ---------------------
  LED(6 downto 0) <= ADDR(6 downto 0);

Process_DRCK1 : process (DRCK1) is
begin
 if (SHIFT='0') or (SEL1='0') then
  ADDR <= "0000000000000000000000000";
 else
   if DRCK1'event and DRCK1 = '0' then
   ADDR <= ADDR + "0000000000000000000000001";
  end if;
 end if;
end process Process_DRCK1;

  Inst_BSCAN : BSCAN_SPARTAN3 port map (
                TDO1 => TDO,
                TDO2 =>  '0',
                DRCK1 => DRCK1,
                DRCK2 => open,
                RESET => RESET,
                SEL1 => SEL1,
                SEL2 => open,
                SHIFT => SHIFT,
                TDI => open,
                UPDATE => open
  );

--------------- cut here --------------------- 

A nice way is to generate a clock enable 1 in N from a counter and use in a 
outer IF statement to enable anything within any given process statement. 
The advantage of this is you can different effective clocks in one design 
but in reality a single clock. This avoids clock boundary crossing, and 
variable timing, issues that can get by generating a clock direct from a 
counter.

Sometimes this will generate a slightly bigger logic size but not 
necessarily as the Spartan-3 flip-flop has effectively a clock enable built 
in. This enable is sometimes used by synthesisers in generating a function 
not immediately thought off as a clock enable but equally not and hence 
"free" to use.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Board.
http://www.enterpoint.co.uk


<u_stadler@yahoo.de> wrote in message 
news:1136280209.379940.143780@o13g2000cwo.googlegroups.com...
> hi
>
> I have a question: what is the proper way to generate c slow clock. I
> have a spartan 3 development board with a 50 MHz external clock. What i
> need is a 4MHz clock for an SPI interface. Since the DCM's can only
> deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to
> devide this clock some more. how is this done properly? a counter? Or
> is ther any other sollution?
>
> Thanks
> Urban
> 

"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag 
news:dpdmcl$6rv$00$1@news.t-online.com...
> Hi,
>
> we all know how to count to 10 right?
>
> I did think I can at least until I did see how
> a binary counter works in Spartan3e - I am still confused:
> the code in FPGA is at the end of the message,
> it really is a very normal counter and should count
>
> 0,1,2,3,4,5,6,7... ?
>
> well it doesnt, it counts
>
> 0,5,2,3,4,1,6,7... !
>
> I have verified this behaviour multiply times and its still
> counting this weird sequence where 1 and 5 are changed.

please dis-regard my prev. posting, it was incorrectly sent as
reply and the issue with the counter seems to be solved it really
is a damaged internal FPGA structure, by floorplanning the
counter into different locations I can produce various
types of wrong counting sequences. So issue solved I think.

Antti 

Urban,

The CLKDV output of the DCM provides a divided version output of the 
clock going in.  DV values of up to 15 are possible.

So, for 4 MHz out, you could have 60 MHz in (and divide by 15).

Or, 4 MHz out, 40 MHz in, DV=10, and so on.

Austin

u_stadler@yahoo.de wrote:

> hi
> 
> I have a question: what is the proper way to generate c slow clock. I
> have a spartan 3 development board with a 50 MHz external clock. What i
> need is a 4MHz clock for an SPI interface. Since the DCM's can only
> deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to
> devide this clock some more. how is this done properly? a counter? Or
> is ther any other sollution?
> 
> Thanks
> Urban
> 

u_stadler@yahoo.de wrote:

> hi
> 
> I have a question: what is the proper way to generate c slow clock. I
> have a spartan 3 development board with a 50 MHz external clock. What i
> need is a 4MHz clock for an SPI interface. Since the DCM's can only
> deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to
> devide this clock some more. how is this done properly? a counter? Or
> is ther any other sollution?
> 
> Thanks
> Urban
> 

The DCM has a clkdv output which will allow you to get 4 MHz directly 
out of the DCM without violating the minimum frequency constraints.

Urban,
Here's another idea to add to your thread!
Divide the 50MHz by 16 with a 4 bit counter and run the SPI interface at 
3.125MHz.
Cheers, Syms. 

u_stadler@yahoo.de wrote:

>hi
>
>I have a question: what is the proper way to generate c slow clock. I
>have a spartan 3 development board with a 50 MHz external clock. What i
>need is a 4MHz clock for an SPI interface. Since the DCM's can only
>deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to
>devide this clock some more. how is this done properly? a counter? Or
>is ther any other sollution?
>  
>
There are 2 ways to go.  You can run the 50 MHz clock to all FFs, and use
a couple FFs to make a divider to 4 MHz.  Of course, there is no integer
relationship between 50 and 4 - somewhat of a problem there.  You might
double the 50 Mhz with a PLL, then divide that by 25 to get your 4 MHz.
The 4 Mhz can be used to generate a one-clock-cycle true pulse every
250 ns and used to enable all the FFs that need the 4 MHz clock.  This
doesn't require skew control, but using a global  clock line might save
routing resources.

The other way is to make the same divider arrangement, and route it over to
one of the global clock drivers, and distribute the 4 MHz clock  to where
it is needed.

Jon

Could somebody also show a little example
how to use this DCM-goodie in practice,
on Spartan-3 (the Starter Kit, that I use...)?
That is, I'd like to know what exactly I need to
write into the Verilog-source and/or UCF-file
to get the CLK divided or multiplied by two,
for example. That is, how to do it purely "textually",
as I have only ISE 7 WebPack, without anything fancy
like FPGA Editor.
I guess I have just to instantiate the "DCM module"
in the main module, and then pass the divided or
multiplied clock signal to other clock-using modules
as their default clock, without needing to do any changes
to them, right?

I'm sure this is explained somewhere at Xilinx
application notes, but they are not really organized
for the easiest perusal, IMHO.

Any help appreciated,

Veli Igor