Schematic Entry, Xilinx or Altera?

Greetings.

I'm looking at doing some basic CPLD designs via Schematic Entry.  Who
has easier to learn/use schematic entry software, Xilinx or Altera?
Both companies have CPLD's that meet my criteria, and design
portability isn't an issue.  Thank you.

> I'm looking at doing some basic CPLD designs via Schematic Entry.  Who
> has easier to learn/use schematic entry software, Xilinx or Altera?

Altera

Regards,

Thomas 

Parkov wrote:

> I'm looking at doing some basic CPLD designs via Schematic Entry.  Who
> has easier to learn/use schematic entry software, Xilinx or Altera?

Altera Quartus.

        -- Mike Treseler

Parkov,

I would invest my time in learning a HDL:  VHDL or Verilog.

Schematic entry for logic design is (almost) completely dead.  It has 
become rare to find anyone doing anything in schematic form, except for 
the highest level where the pins are connected.

All of the levels of logic are described in hardware design language 
(HDL) modules.

To pick a vendor based on their 'schematic tool' is probably the least 
interesting criteria.

Picking the vendor based on:

-available technology
-speed
-power
-features
-cost
-size
-package
-ease of use of software tools
-available synthesis tools
-available simulators
-FAE support
-web support
-part availability

all makes sense.

Austin

Austin Lesea wrote:

> I would invest my time in learning a HDL:  VHDL or Verilog.

Good advice, but allow several months.

> Schematic entry for logic design is (almost) completely dead.  It has 
> become rare to find anyone doing anything in schematic form, except for 
> the highest level where the pins are connected.

The one place it isn't dead is for
circuit-board oriented, first-time
cpld users copying some glue logic
off of an application note.

      -- Mike Treseler

>The one place it isn't dead is for
>circuit-board oriented, first-time
>cpld users copying some glue logic
>off of an application note.

Thats about where I'm at.  No worries, I'm checking out the two HDL
variants, just wanted to get a couple things rolling fast in the
meantime.  I'm coming from a 74xxx chip to chip background so I already
have some designs on paper.  Thanks for the heads up everyone on the
Quartus recomendation.

Mike Treseler <mike_treseler@comcast.net> wrote:
> Austin Lesea wrote:

> > I would invest my time in learning a HDL:  VHDL or Verilog.

> Good advice, but allow several months.

But schematic entry oftem leads to non-registered designs, where you should
allow several month of debugging too... 
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Parkov wrote:
> >The one place it isn't dead is for
> >circuit-board oriented, first-time
> >cpld users copying some glue logic
> >off of an application note.
>
> Thats about where I'm at.  No worries, I'm checking out the two HDL
> variants, just wanted to get a couple things rolling fast in the
> meantime.  I'm coming from a 74xxx chip to chip background so I already
> have some designs on paper.  Thanks for the heads up everyone on the
> Quartus recomendation.

And be sure to try out the 7400 series library that is provided with
Quartus too, to make your transition easier. Once you have your design
working use the Quartus builtin Verilog or VHDL synthesizer to expand
your knowledge of FPGA design.

Quartus allows mixed mode designs so that you can create design blocks
as a schematic or HDL.

Hope this helps,
Subroto Datta
Altera Corp.

Uwe Bonnes wrote:

> But schematic entry oftem leads to non-registered designs, where you should
> allow several month of debugging too... 

I was playing the OP's advocate here,
because I started out where he is now.

Certainly HDL is the clean way to go.
But I also know that many hardware guys
will try it the "quick" way first.

      -- Mike Treseler

Parkov wrote:
>>The one place it isn't dead is for
>>circuit-board oriented, first-time
>>cpld users copying some glue logic
>>off of an application note.
> 
> 
> Thats about where I'm at.  No worries, I'm checking out the two HDL
> variants, just wanted to get a couple things rolling fast in the
> meantime.  I'm coming from a 74xxx chip to chip background so I already
> have some designs on paper.  Thanks for the heads up everyone on the
> Quartus recomendation.

There is also a 'middle ground', between VHDL and Schematics :

Use a Boolean Eqn language, such as

Xilinx have ABEL  ( but for CPLD only, which here is OK ),
Altera have  AHDL ( I think still alive for CPLD ? )
Atmel have WinCUPL for CPLD, includes functional simulation, so can 
create test vectors, to allow 100% chip functional test at PGM time.
This flow works best on smaller PLDs that are pgmd off-board.

Lattice also have ABEL, not sure on their plans for ABEL-MachXO support 
? There is a large installed base of ABEL/Boolean EQN code for CPLDs,
so if they want to migrate those designs to MachXO, that would be
an important flow.

ICT have WinPLACE


If you start to need timing simulation, then you need to align to the 
simulation tools.

What complexity/package of CPLD do you expect to use ?

-jg