So I need some help getting started with programmable logic and VHDL. In the past all I have done in the programmable logic area are 16V8 and 22V10 PALs. I actually feel kind of stupid about the simple questions I am about to ask, since it isn't like I don't know a lot about electonics. I have a BSEE and in the past I've designed DSP boards and motor controllers that control hundreds of amps and make electric forklifts able to lift thousands of pounds. Pretty fun stuff actually. But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and the Xilinx XC9536XL experimenter board I am using. I've gone through ALDEC's Evita VHDL tutoral end to end and I think I've learned the basics of the language. So my project was to write a program to take a step and direction input and output the proper sequences to control a stepper motor. But the logic output sequences I got didn't make sense, so I decided to walk before I run and just programmed up a couple very simple programs. More on that later. So what I've got is an XC9536XL board I bought on eBay. I connected a 4 position dip switch with 4 pull up resistors connected so that when you turn on a switch the input is grounded and read as a zero. Turn off the switch and the pullup pulls high and it's read as a one. I know this works because I can measure the correct logic signal right at the CPLD. I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through a current limiting resistor. The other end of each LED is connected to an output of the CPLD. So sending a logic zero to the output should sink current and turn on the LED. The LEDs work because I can unplug them from the socket header and connect each to ground and the LED lights as expected. The first "simple" program I wrote was to read the switch inputs and output them to the LEDs, using the following VHDL code in Xilinx ISE 7.1: ---------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Test1 is Port (SWITCH_IN : in std_logic_vector(3 downto 0); LEDS_OUT : out std_logic_vector(3 downto 0)); end Test1; architecture Behavioral of Test1 is begin LEDS_OUT <= SWITCH_IN; end Behavioral; ---------------------- This code shows that the LEDs and switches work. I can flip the switches and the LEDs change state. But here is the first problem. The LEDs light opposite what I expect. The LEDs light when the corresponding switch is set to input a high into the CPLD. It's like either the inputs or outputs are being inverted inside the CPLD. So I thought I'd try something simpler -- to turn on all the LEDs by outputting "0000" to the four pins the LEDs are connected to. I changed the LEDS_OUT assignment to LEDS_OUT <= "0000"; expecting the LEDs to turn on. They didn't. So I figured maybe the outputs are what's being inverted. I changed it to LEDS_OUT <= "1010"; thinking that this way, inverted or not, two LEDs would light and two wouldn't. The problem is none of the LEDs light. Remember that I showed that both the switches and LEDs can change state with LEDS_OUT <= SWITCH_IN;, just backwards from what I expected. So I remembered from the tutorial that lots of code in VHDL is triggered by changes in inputs, so I changed the LEDS_OUT assignment to the following: LEDS_OUT <= "101" & (SWITCH_IN(3) and SWITCH_IN(2) and SWITCH_IN(1) and SWITCH_IN(0)); This should kill two birds with one stone. It will show me if I can assign pins directly to values when it is part of an equation that includes inputs that can change state. I thought mabye my previous attempts didn't work since there was nothing to "trigger" the equation. Also, with ANDing the switches and outputting that to one LED, I can tell if it is the inputs or the outputs that are being inverted inside the CPLD. If it is the inputs, I would have to set the switches to all input a zero before the AND will be active and change the state of the LED. "0000" will be the input that causes a different output then the other 15 combinations, insted of "1111." If it is the output being inverted, I'd have to set the inputs all to one, but the LED will light opposite of what I expect, turning on with the inputs all set to one (remember the output sinks current from the LED and therefore the LED lights when a zero is output). The result is that the upper 3 LEDs still all remain off, despite directly setting two outputs to a one and one output to a zero. My logic probe shows a high on those three CPLD pins. Apparently I can't directly set a pin even when it is part of an equation. The last LED lights when all four switch inputs are set to input a high. This indicates that the inputs are not being inverted in the CPLD. But the LED lights when the switches are all set high and I can measure a logic low, 0V, on that LED's pin. This would indicate that the outputs are being inverted from the way the assignment equation would indicate. My next experiment was to do something simple - a 4 bit counter right from the Xilinx language templates. I ended up with the following VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Counter1 is Port ( CLK_IN : std_logic; SWITCH_IN : in std_logic_vector(3 downto 0); LEDS_OUT : out std_logic_vector(3 downto 0)); end Counter1; architecture Behavioral of Counter1 is signal count : std_logic_vector(3 downto 0) := "0000"; begin process (CLK_IN) begin if CLK_IN = '1' and CLK_IN'event then if SWITCH_IN(0)='1' then count <= count + 1; else count <= count - 1; end if; end if; end process; LEDS_OUT <= count; end Behavioral; In the simulator this counter works fine, but when I run this code the output sequence I get is not a straight count from 0 to 15. I get the sequence 0,1,14,3,12,5,10,7,8,9,6,11,4,13,3,15. It is perfectly repeatable, and the sequence reverses when I flip SWITCH_IN(0). After some looking at the binary for that count sequence, I noticed that every second number is the inverse of the previous, instead of the expected number (14 is 1110, inverse of 0001 that preceeded it, not 0010 as expected next). I don't get it. So my questions are: 1. When I do LEDS_OUT <= SWITCH_IN; why does there appear to be an inversion happening somewhere inside the CPLD, apparently at the outputs? 2. Why can't I just set outputs to a zero and have a LED light? Any pin I directly assign to a value stays high. 3. Why doesn't my counter count? It shouldn't be this difficult... This ended up a lot longer than I expected, so if you made it this far, thanks for reading it, and thanks for any help you can provide... cdsmith
Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
Started by ●January 5, 2006
Reply by ●January 5, 20062006-01-05
cdsmith69@gmail.com wrote:> So I need some help getting started with programmable logic and VHDL. > > In the past all I have done in the programmable logic area are 16V8 and > 22V10 PALs. > > I actually feel kind of stupid about the simple questions I am about to > ask, since it isn't like I don't know a lot about electonics. I have a > BSEE and in the past I've designed DSP boards and motor controllers > that control hundreds of amps and make electric forklifts able to lift > thousands of pounds. Pretty fun stuff actually. > > But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and > the Xilinx XC9536XL experimenter board I am using.What did you use to design the 16V8/22V10's ? Why not use ABEL, for the 9536 ? -jg
Reply by ●January 5, 20062006-01-05
cdsmith69@gmail.com wrote:> So I need some help getting started with programmable logic and VHDL. > > In the past all I have done in the programmable logic area are 16V8 and > 22V10 PALs. > > I actually feel kind of stupid about the simple questions I am about to > ask, since it isn't like I don't know a lot about electonics. I have a > BSEE and in the past I've designed DSP boards and motor controllers > that control hundreds of amps and make electric forklifts able to lift > thousands of pounds. Pretty fun stuff actually. > > But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and > the Xilinx XC9536XL experimenter board I am using. > > I've gone through ALDEC's Evita VHDL tutoral end to end and I think > I've learned the basics of the language. > > So my project was to write a program to take a step and direction input > and output the proper sequences to control a stepper motor. But the > logic output sequences I got didn't make sense, so I decided to walk > before I run and just programmed up a couple very simple programs. > More on that later. > > So what I've got is an XC9536XL board I bought on eBay. I connected a > 4 position dip switch with 4 pull up resistors connected so that when > you turn on a switch the input is grounded and read as a zero. Turn > off the switch and the pullup pulls high and it's read as a one. I > know this works because I can measure the correct logic signal right at > the CPLD. > > I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through > a current limiting resistor. The other end of each LED is connected to > an output of the CPLD. So sending a logic zero to the output should > sink current and turn on the LED. The LEDs work because I can unplug > them from the socket header and connect each to ground and the LED > lights as expected.This is typically how LEDs are connected to a CPLD. VCC should be +3.3 volts, since the XC9536XL is a 3.3 volt part (with 5-volt tolerant I/O's). So, in order to turn on an LED, the CPLD needs to ground the LED's lead. (BTW: the LED is -->|-- ) so: [+3.3]-----[R]--->|---- [CPLD pin, or ground.] LED> > The first "simple" program I wrote was to read the switch inputs and > output them to the LEDs, using the following VHDL code in Xilinx ISE > 7.1: > > ---------------------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity Test1 is > Port (SWITCH_IN : in std_logic_vector(3 downto 0); > LEDS_OUT : out std_logic_vector(3 downto 0)); > end Test1; > > architecture Behavioral of Test1 is > begin > LEDS_OUT <= SWITCH_IN; > end Behavioral; > ----------------------If you had inverted the switches, then you should have seen the expected behaviour: LEDS_OUT <= not SWITCH_IN;> > This code shows that the LEDs and switches work. I can flip the > switches and the LEDs change state. But here is the first problem. > The LEDs light opposite what I expect. The LEDs light when the > corresponding switch is set to input a high into the CPLD. It's like > either the inputs or outputs are being inverted inside the CPLD. > > So I thought I'd try something simpler -- to turn on all the LEDs by > outputting "0000" to the four pins the LEDs are connected to. I > changed the LEDS_OUT assignment to LEDS_OUT <= "0000"; expecting the > LEDs to turn on. They didn't. So I figured maybe the outputs are > what's being inverted. I changed it to LEDS_OUT <= "1010"; thinking > that this way, inverted or not, two LEDs would light and two wouldn't. > The problem is none of the LEDs light. Remember that I showed that > both the switches and LEDs can change state with LEDS_OUT <= > SWITCH_IN;, just backwards from what I expected. > > So I remembered from the tutorial that lots of code in VHDL is > triggered by changes in inputs, so I changed the LEDS_OUT assignment to > the following: > > LEDS_OUT <= "101" & (SWITCH_IN(3) and SWITCH_IN(2) and SWITCH_IN(1) > and SWITCH_IN(0)); > > This should kill two birds with one stone. It will show me if I can > assign pins directly to values when it is part of an equation that > includes inputs that can change state. I thought mabye my previous > attempts didn't work since there was nothing to "trigger" the equation. > > Also, with ANDing the switches and outputting that to one LED, I can > tell if it is the inputs or the outputs that are being inverted inside > the CPLD. If it is the inputs, I would have to set the switches to all > input a zero before the AND will be active and change the state of the > LED. "0000" will be the input that causes a different output then the > other 15 combinations, insted of "1111." If it is the output being > inverted, I'd have to set the inputs all to one, but the LED will light > opposite of what I expect, turning on with the inputs all set to one > (remember the output sinks current from the LED and therefore the LED > lights when a zero is output). > > The result is that the upper 3 LEDs still all remain off, despite > directly setting two outputs to a one and one output to a zero. My > logic probe shows a high on those three CPLD pins. Apparently I can't > directly set a pin even when it is part of an equation. > > The last LED lights when all four switch inputs are set to input a > high. This indicates that the inputs are not being inverted in the > CPLD. But the LED lights when the switches are all set high and I can > measure a logic low, 0V, on that LED's pin. This would indicate that > the outputs are being inverted from the way the assignment equation > would indicate. > > My next experiment was to do something simple - a 4 bit counter right > from the Xilinx language templates. I ended up with the following VHDL > code: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity Counter1 is > Port ( CLK_IN : std_logic; > SWITCH_IN : in std_logic_vector(3 downto 0); > LEDS_OUT : out std_logic_vector(3 downto 0)); > end Counter1; > > architecture Behavioral of Counter1 is > signal count : std_logic_vector(3 downto 0) := "0000"; > begin > process (CLK_IN) > begin > if CLK_IN = '1' and CLK_IN'event then > if SWITCH_IN(0)='1' then > count <= count + 1; > else > count <= count - 1; > end if; > end if; > end process; > LEDS_OUT <= count; > end Behavioral; > > > In the simulator this counter works fine, but when I run this code the > output sequence I get is not a straight count from 0 to 15. I get the > sequence 0,1,14,3,12,5,10,7,8,9,6,11,4,13,3,15. It is perfectly > repeatable, and the sequence reverses when I flip SWITCH_IN(0). After > some looking at the binary for that count sequence, I noticed that > every second number is the inverse of the previous, instead of the > expected number (14 is 1110, inverse of 0001 that preceeded it, not > 0010 as expected next). I don't get it. > > > So my questions are: > 1. When I do LEDS_OUT <= SWITCH_IN; why does there appear to be an > inversion happening somewhere inside the CPLD, apparently at the > outputs? > 2. Why can't I just set outputs to a zero and have a LED light? Any > pin I directly assign to a value stays high.You should be able to assign a 0 to each LED pin, and that should cause each LED to lite. LEDS_OUT <= "0000"; or LEDS_OUT <= (others => '0');> 3. Why doesn't my counter count?Hmm... I'm a bit puzzled by this, too. Try making an up counter. Modify your code to count up only, and to not check the switch. Also, the perferred way to act on a rising edge clock is if rising_edge( CLK_in ) then Also:IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED are non-standard libraries. You're better off using IEEE.NUMERIC_STD, instead. Out of curiousity, where does CLK_in come from and what is its frequency? And do you know that your LEDS_OUT CPLD pins are actually connected to the LEDs and not something else? After you've synthesized the code, look at the FITTER report. At the end of the report, it shows list of chip pins and the name that has been assigned to each chip pin. If they are wrong, you will need a UCF (User Constraint File). The simplest way to do this is to find the UCF that came with you board, and then select PROJECT->ADD Source and supply the name of the UCF. If there is no UCF file, then you'll have to create one. The Process box should show USER CONTRAINTS. Click on the [+] to expand it and click on ASSIGN PACKAGE PINS. This will bring up another screen that shows a drawing of the chip, plus a list of signals. It's then an easy matter of assigning your signals to the chip so that the signal match up with how the chip is wired on the board.> > It shouldn't be this difficult... > > This ended up a lot longer than I expected, so if you made it this far, > thanks for reading it, and thanks for any help you can provide... > > cdsmith"thanks for reading it" You're welcome. I had a lot of problems like this when I was just starting out, too. And who knows, perhaps the board you bought from eBay has problems. HTH -Dave Pollum
Reply by ●January 5, 20062006-01-05
cdsmith69@gmail.com wrote:> So I need some help getting started with programmable logic and VHDL. > > In the past all I have done in the programmable logic area are 16V8 and > 22V10 PALs. > > I actually feel kind of stupid about the simple questions I am about to > ask, since it isn't like I don't know a lot about electonics. I have a > BSEE and in the past I've designed DSP boards and motor controllers > that control hundreds of amps and make electric forklifts able to lift > thousands of pounds. Pretty fun stuff actually. > > But I am stumped by a few simple things with VHDL, Xilinx ISE 7.1, and > the Xilinx XC9536XL experimenter board I am using. > > I've gone through ALDEC's Evita VHDL tutoral end to end and I think > I've learned the basics of the language. > > So my project was to write a program to take a step and direction input > and output the proper sequences to control a stepper motor. But the > logic output sequences I got didn't make sense, so I decided to walk > before I run and just programmed up a couple very simple programs. > More on that later. > > So what I've got is an XC9536XL board I bought on eBay. I connected a > 4 position dip switch with 4 pull up resistors connected so that when > you turn on a switch the input is grounded and read as a zero. Turn > off the switch and the pullup pulls high and it's read as a one. I > know this works because I can measure the correct logic signal right at > the CPLD. > > I also connected 4 LEDs. The 4 LEDs are each connected to Vcc through > a current limiting resistor. The other end of each LED is connected to > an output of the CPLD. So sending a logic zero to the output should > sink current and turn on the LED. The LEDs work because I can unplug > them from the socket header and connect each to ground and the LED > lights as expected.This is typically how LEDs are connected to a CPLD. VCC should be +3.3 volts, since the XC9536XL is a 3.3 volt part (with 5-volt tolerant I/O's). So, in order to turn on an LED, the CPLD needs to ground the LED's lead. (BTW: the LED is -->|-- ) so: [+3.3]-----[R]--->|---- [CPLD pin, or ground.] LED> > The first "simple" program I wrote was to read the switch inputs and > output them to the LEDs, using the following VHDL code in Xilinx ISE > 7.1: > > ---------------------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity Test1 is > Port (SWITCH_IN : in std_logic_vector(3 downto 0); > LEDS_OUT : out std_logic_vector(3 downto 0)); > end Test1; > > architecture Behavioral of Test1 is > begin > LEDS_OUT <= SWITCH_IN; > end Behavioral; > ----------------------If you had inverted the switches, then you should have seen the expected behaviour: LEDS_OUT <= not SWITCH_IN;> > This code shows that the LEDs and switches work. I can flip the > switches and the LEDs change state. But here is the first problem. > The LEDs light opposite what I expect. The LEDs light when the > corresponding switch is set to input a high into the CPLD. It's like > either the inputs or outputs are being inverted inside the CPLD. > > So I thought I'd try something simpler -- to turn on all the LEDs by > outputting "0000" to the four pins the LEDs are connected to. I > changed the LEDS_OUT assignment to LEDS_OUT <= "0000"; expecting the > LEDs to turn on. They didn't. So I figured maybe the outputs are > what's being inverted. I changed it to LEDS_OUT <= "1010"; thinking > that this way, inverted or not, two LEDs would light and two wouldn't. > The problem is none of the LEDs light. Remember that I showed that > both the switches and LEDs can change state with LEDS_OUT <= > SWITCH_IN;, just backwards from what I expected. > > So I remembered from the tutorial that lots of code in VHDL is > triggered by changes in inputs, so I changed the LEDS_OUT assignment to > the following: > > LEDS_OUT <= "101" & (SWITCH_IN(3) and SWITCH_IN(2) and SWITCH_IN(1) > and SWITCH_IN(0)); > > This should kill two birds with one stone. It will show me if I can > assign pins directly to values when it is part of an equation that > includes inputs that can change state. I thought mabye my previous > attempts didn't work since there was nothing to "trigger" the equation. > > Also, with ANDing the switches and outputting that to one LED, I can > tell if it is the inputs or the outputs that are being inverted inside > the CPLD. If it is the inputs, I would have to set the switches to all > input a zero before the AND will be active and change the state of the > LED. "0000" will be the input that causes a different output then the > other 15 combinations, insted of "1111." If it is the output being > inverted, I'd have to set the inputs all to one, but the LED will light > opposite of what I expect, turning on with the inputs all set to one > (remember the output sinks current from the LED and therefore the LED > lights when a zero is output). > > The result is that the upper 3 LEDs still all remain off, despite > directly setting two outputs to a one and one output to a zero. My > logic probe shows a high on those three CPLD pins. Apparently I can't > directly set a pin even when it is part of an equation. > > The last LED lights when all four switch inputs are set to input a > high. This indicates that the inputs are not being inverted in the > CPLD. But the LED lights when the switches are all set high and I can > measure a logic low, 0V, on that LED's pin. This would indicate that > the outputs are being inverted from the way the assignment equation > would indicate. > > My next experiment was to do something simple - a 4 bit counter right > from the Xilinx language templates. I ended up with the following VHDL > code: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity Counter1 is > Port ( CLK_IN : std_logic; > SWITCH_IN : in std_logic_vector(3 downto 0); > LEDS_OUT : out std_logic_vector(3 downto 0)); > end Counter1; > > architecture Behavioral of Counter1 is > signal count : std_logic_vector(3 downto 0) := "0000"; > begin > process (CLK_IN) > begin > if CLK_IN = '1' and CLK_IN'event then > if SWITCH_IN(0)='1' then > count <= count + 1; > else > count <= count - 1; > end if; > end if; > end process; > LEDS_OUT <= count; > end Behavioral; > > > In the simulator this counter works fine, but when I run this code the > output sequence I get is not a straight count from 0 to 15. I get the > sequence 0,1,14,3,12,5,10,7,8,9,6,11,4,13,3,15. It is perfectly > repeatable, and the sequence reverses when I flip SWITCH_IN(0). After > some looking at the binary for that count sequence, I noticed that > every second number is the inverse of the previous, instead of the > expected number (14 is 1110, inverse of 0001 that preceeded it, not > 0010 as expected next). I don't get it. > > > So my questions are: > 1. When I do LEDS_OUT <= SWITCH_IN; why does there appear to be an > inversion happening somewhere inside the CPLD, apparently at the > outputs? > 2. Why can't I just set outputs to a zero and have a LED light? Any > pin I directly assign to a value stays high.You should be able to assign a 0 to each LED pin, and that should cause each LED to lite. LEDS_OUT <= "0000"; or LEDS_OUT <= (others => '0');> 3. Why doesn't my counter count?Hmm... I'm a bit puzzled by this, too. Try making an up counter. Modify your code to count up only, and to not check the switch. Also, the perferred way to act on a rising edge clock is if rising_edge( CLK_in ) then Also:IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED are non-standard libraries. You're better off using IEEE.NUMERIC_STD, instead. Out of curiousity, where does CLK_in come from and what is its frequency? And do you know that your LEDS_OUT CPLD pins are actually connected to the LEDs and not something else? After you've synthesized the code, look at the FITTER report. At the end of the report, it shows list of chip pins and the name that has been assigned to each chip pin. If they are wrong, you will need a UCF (User Constraint File). The simplest way to do this is to find the UCF that came with you board, and then select PROJECT->ADD Source and supply the name of the UCF. If there is no UCF file, then you'll have to create one. The Process box should show USER CONTRAINTS. Click on the [+] to expand it and click on ASSIGN PACKAGE PINS. This will bring up another screen that shows a drawing of the chip, plus a list of signals. It's then an easy matter of assigning your signals to the chip so that the signal match up with how the chip is wired on the board.> > It shouldn't be this difficult... > > This ended up a lot longer than I expected, so if you made it this far, > thanks for reading it, and thanks for any help you can provide... > > cdsmith"thanks for reading it" You're welcome. I had a lot of problems like this when I was just starting out, too. And who knows, perhaps the board you bought from eBay has problems. HTH -Dave Pollum
Reply by ●January 5, 20062006-01-05
>What did you use to design the 16V8/22V10's ? >Why not use ABEL, for the 9536 ? >-jgMost commonly was ICT pals with their WinPlace software, but I did use some AMD pals and their ABEL software, way back in about 1995. Neither of these programs will work for the 9536.
Reply by ●January 5, 20062006-01-05
I've got to get a real newsreader set up insted of using google groups. :-)> so: [+3.3]-----[R]--->|---- [CPLD pin, or ground.] > LEDYup, this is now it is wired. I did that because I noticed that the 9536 can sink a lot more current than it can source.>If you had inverted the switches, then you should have >seen the expected behaviour: > LEDS_OUT <= not SWITCH_IN;I realize that, but I hate doing things like that without understanding why it needs to be done. In the old days when I did PALs the software I used then allowed you to specify a pin as active low, and when an equation came out true, the pin would go low. If I saw something in the documenation like that I would be satisfied and would throw in the not... :-)>You should be able to assign a 0 to each LED pin, and >that should cause each LED to lite. > LEDS_OUT <= "0000"; or LEDS_OUT <= (others => '0');I tried LEDS_OUT <= "0000" thinking they would all light, but they didn't. I then tried LEDS_OUT <= "1111" thinking that would work if the outputs were being inverted. No dice. So I tried LEDS_OUT <= "1010" thinking two would light and two wouldn't, I don't care which for now, I just want to see something light up. But nothing happens. :-(>> 3. Why doesn't my counter count? >Hmm... I'm a bit puzzled by this, too. Try making an up counter.Will do, tonight.> Also, the perferred way to act on a rising edge clock is > if rising_edge( CLK_in ) thenI'll switch to that and see if it makes a difference. I did it the other way because that is what they always did it in the ALDEC VHDL tutorial I learned from.>Also:IEEE.STD_LOGIC_ARITH and IEEE.STD_LOGIC_UNSIGNED are non-standard >libraries. You're better off using IEEE.NUMERIC_STD, instead.Those were thrown in there by the Xilinx software when I created a new project. Being new to VHDL, I don't really understand what comes from what libraries yet. :-)>Out of curiousity, where does CLK_in come from and >what is its frequency?It comes from my function generator. Square wave output set to 3.3V. Looks clean on my oscilloscope. I had the frequency low enough that I could watch the count sequence on the LEDS, like around 1Hz.>And do you know that your LEDS_OUT CPLD pins are actually >connected to the LEDs and not something else?Because the expected LEDS do light when I flip switches with "LEDS_OUT <= SWITCH_IN. It's just the polarity in opposite what I expect. Plus, I looked at the board layout to be sure, and took an ohm meter right from the CPLD pins to the header and it measured connected properly. I did do a UCF to assign the pins because I had already wired everything up before I even wrote the program. Which brings up another question. Does it matter if I put CLK on one of the global clock pins? I didn't at first, but moved to to one later. It didn't seem to make any difference on the counter's behavior.>And who knows, perhaps the >board you bought from eBay has problems.Yeah. The company I bought it from has been selling it for years, but I guess that doesn't mean it's guaranteed to work right. I was looking at it since my original post and I realized that it doesn't really have proper bypass capacitors on it. There's just one 100uF electrolytic cap near the CPLD. I suppose if that is causing power problems then I might see issues with things like counters, but not with simple things like running the switches right to the LEDS. I think I'm going to tack solder a few bypass caps to the bottom and see if that changes anything. Thanks for the help. If I figure it all out I'll post here so everyone knows what was wrong.
Reply by ●January 5, 20062006-01-05
cdsmith69@gmail.com wrote:> So I need some help getting started with programmable logic and VHDL. > > It shouldn't be this difficult...My guess is that you haven't defined which pin on the outside of your CPLD is connected to which signal on the inside of your CPLD. You've ended up with random signals to random pins, defined by the fitting tool to whatever made it's life easiest. The mapping will change every time you modify and resysnthesise the code. You need to add a .ucf file to your project with the signal->pin mappings in it. It's just a text file, the format should look something similar to the following: # DSP bus interface NET "XA<0>" LOC = "p128"; NET "XA<1>" LOC = "p102"; NET "XA<2>" LOC = "p89"; NET "XINT1" LOC = "p130"; NET "CSn" LOC = "p100"; NET "RDn" LOC = "p103"; The .ucf file is also where you add your timing constraints, you should at least have one for your clock (when you're using one). That section will look like: # Timing constraints NET "CLOCK" TNM_NET = "CLOCK"; TIMESPEC "TS_CLOCK" = PERIOD "CLOCK" 8 ns HIGH 50 %; NET "CLOCK" USELOWSKEWLINES; These constraints have been cut from an FPGA project .ucf file, but I'm pretty sure that the syntax is the same for CPLDs. Hope this helps! Cheers, James
Reply by ●January 5, 20062006-01-05
cdsmith69@gmail.com wrote:>>What did you use to design the 16V8/22V10's ? >>Why not use ABEL, for the 9536 ? >>-jg > > > Most commonly was ICT pals with their WinPlace software, but I did use > some AMD pals and their ABEL software, way back in about 1995. > > Neither of these programs will work for the 9536.You do realize Xilinx has ABEL flows for their CPLDs ? [ Scan for .ABL files, in their examples directories] You'll find the learning curve much shorter, and ABEL is fine at the smaller end of the scale.
Reply by ●January 6, 20062006-01-06
The solution is simple, but far from obvious. You need to download and apply the patch for ISE 7.1 or install the latest service pack (4). There is a bug that inverts all of the outputs of CPLDs (with no service pack and also maybe SP1). Go to www.xilinx.com, select downloads, log in (or create a new account), then select your ISE version and OS. Xilinx has refused to post this information to their download page. I even talked to a factory FAE and he could not get them to post it. The only way you can find out about it is to search their site for key words that match the article. Marc
Reply by ●January 6, 20062006-01-06
I think what you need is a design flow/ISE tutor document, it's somewhere on Xilinx web. Some more suggestions: Try using simulator (Model sim or Xilinx Sim in 7.1) Read the fitter report to see the implemented equations Also try the ChipViewer to see internal signals After all of these verification steps are done and the board still won't work as expected, Check your configuration method (JTAG? ), verify if your *.jed file has been loaded correctly? Now, you may think of a hardware issue Cheers,
