PCI compliance ?

Hello,

I have to design a board with a PCI interface which shall be compliant with
a larg range of PCI versions !
3.3V 32bits / 33Mhz
5V 32bits / 33Mhz
3.3V 64 bits / 66 Mhz

The board should use V2P xilinx FPGA so what bothers me is the 3.3V and 5V
compliance.
Is there a simple solution to achieve this ?

Thanks.

St�phane.

Yes, using external I/O buffer for the I/O of the bus and connecting
them on the V/IO of the PCI bus.

The only compliance problem might be the clock since you must have a
single load on it. Using a zero delay buffer 5 v compliant that should
be possible.

Sylvain Munaut <SomeOne@SomeDomain.com> schrieb:
> Yes, using external I/O buffer for the I/O of the bus and connecting
> them on the V/IO of the PCI bus.
No. We had that on this newsgroup on a regular basis.
The pci standard states explicitly that there may be no discrete
components connected to the signals.
You can not be fully compliant to 5V PCI with a V2P.

It is general consensus to ignore that rule but you better not use the
PCI logo to avoid cease and desist letters of your competitors.

Kolja Sulima

You can use bus switches to limit voltage allowing 5V operation. Technically 
by PCI spec they aren't allowed but we do on our development boards as do a 
number of our competitors and have never seen a problem.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost FPGA Development Board.
http://www.enterpoint.co.uk



"sjulhes" <t@aol.fr> wrote in message 
news:43be196a$0$7176$636a15ce@news.free.fr...
> Hello,
>
> I have to design a board with a PCI interface which shall be compliant 
> with
> a larg range of PCI versions !
> 3.3V 32bits / 33Mhz
> 5V 32bits / 33Mhz
> 3.3V 64 bits / 66 Mhz
>
> The board should use V2P xilinx FPGA so what bothers me is the 3.3V and 5V
> compliance.
> Is there a simple solution to achieve this ?
>
> Thanks.
>
> St&#4294967295;phane.
>
>
> 

On Fri, 06 Jan 2006 10:50:11 +0100, Kolja Sulimma <news@sulimma.de> wrote:

>Sylvain Munaut <SomeOne@SomeDomain.com> schrieb:
>> Yes, using external I/O buffer for the I/O of the bus and connecting
>> them on the V/IO of the PCI bus.
>No. We had that on this newsgroup on a regular basis.
>The pci standard states explicitly that there may be no discrete
>components connected to the signals.

What's their definition of a discrete component..? I suspect they are talking about resistors etc. 
Does it actually say that each signal must go to a single chip ? If not, then I see no problems with
signals going to different (buffer) chips.  

My understanding is that you can only load once each line that's it ...

Mike Harrison schrieb:
> What's their definition of a discrete component..?
> I suspect they are talking about resistors etc.
> Does it actually say that each signal must go to a single chip ?
> If not, then I see no problems with
> signals going to different (buffer) chips.

Sylvain Munaut <SomeOne@SomeDomain.com> schrieb:
> My understanding is that you can only load once each line that's it ...

That is bad enough. Why should a microswitch be a sginificantly lower
load to a signal than an FPGA or ASIC? An IDT quickswitch can have up to
7pF capacitance.


"Section 4.4.3.4 Signal Loading
Shared PCI signals must be limited to one load on the expansion board. [...]
It is specifically a violation of this specification for expansion
boards to:
* Attach an expansion ROM directly (or via bus transceivers) on any PCI pin.
* Attach two or more PCU devices on an expansion board [...]
* Attach any logic [..] that "snoops" PCI pins.
* Use PCI component sets that place more than one load on each PCI pin:
e.g. separate address and data path components.
* Use a PCI component that hast more than 10pF capacitance per pin.
* Attach any pull-up resistors or other discrete devices to the PCI
signals, unless thay are placed *behind* a PCI-to_PCI bridge."


Kolja Sulimma

All,

The PCI standard is written to create and protect ASSP and ASIC device 
sales, and is specifically worded to prevent alternate solutions.

Regardless, FPGAs find there way into many PCI applications.

Austin

Kolja Sulimma wrote:
> Mike Harrison schrieb:
> 
>>What's their definition of a discrete component..?
>>I suspect they are talking about resistors etc.
>>Does it actually say that each signal must go to a single chip ?
>>If not, then I see no problems with
>>signals going to different (buffer) chips.
> 
> 
> Sylvain Munaut <SomeOne@SomeDomain.com> schrieb:
> 
>>My understanding is that you can only load once each line that's it ...
> 
> 
> That is bad enough. Why should a microswitch be a sginificantly lower
> load to a signal than an FPGA or ASIC? An IDT quickswitch can have up to
> 7pF capacitance.
> 
> 
> "Section 4.4.3.4 Signal Loading
> Shared PCI signals must be limited to one load on the expansion board. [...]
> It is specifically a violation of this specification for expansion
> boards to:
> * Attach an expansion ROM directly (or via bus transceivers) on any PCI pin.
> * Attach two or more PCU devices on an expansion board [...]
> * Attach any logic [..] that "snoops" PCI pins.
> * Use PCI component sets that place more than one load on each PCI pin:
> e.g. separate address and data path components.
> * Use a PCI component that hast more than 10pF capacitance per pin.
> * Attach any pull-up resistors or other discrete devices to the PCI
> signals, unless thay are placed *behind* a PCI-to_PCI bridge."
> 
> 
> Kolja Sulimma

austin wrote:
>
> The PCI standard is written to create and protect ASSP and ASIC device
> sales, and is specifically worded to prevent alternate solutions.
>
  Does Xilinx marketing pay you a bounty each time you make such
an absurd claim on comp.arch.fpga?

  The PCI specs are written to guarantee interoperability across
best/worst case device/backplane loading and topologies.

  That the required bus loading excludes FPGA vendors who haven't
improved their Cin specs since their first family of 20+ years ago is
certainly not the fault of the standards.

Brian

Brian,

I am paid (in very small part) to watch this newsgroup, and comment.

As for 'absurd claim', it seems you have never served on a standards 
body, as your comment has me laughing.

A 'standard' serves the interests of the companies that promoted it (as 
well as providing a service to the industry).  There is active work by 
any standards committee to exclude/disadvantage/hobble as many 
competitors as possible (legally).

I used to call it "making every participant equally disadvantaged in 
order to level the playing field as much as possible prior to approval."

A great example of this is when an ASIC is developed, and the company 
that has it, promotes it as a standard.  In the process of getting it 
approved, it is inevitable that the standard will require a respin of 
the silicon in order that all vendors have a chance to participate.  The 
original vendor must also respin their chip, as they are not "standard" 
until they do so.

I have seen this multiple times in my 13 years of sitting on multiple 
ANSI/ATIS/IEEE/IEC standards committees.

Since you don't know this, I suggest you go and volunteer to chair a 
committee, and learn something about the real world.

Austin