FPGA Journal Article

"Hahnsolo" <coreyhahn@gmail.com> schrieb im Newsbeitrag 
news:1137338637.940229.315040@g49g2000cwa.googlegroups.com...
> Well, I guess I would be one of those "rebirth" hobbyists.  I am
> younger and just "discovered" the fpga.  I was under the impression
> that things like this were very expensive, but when I see starter kits
> for $150, I had to snatch one up and try it out.  For the last 5 months
> I have been feverishly programming and learning with Webpack 7.1
> implimenting different ideas on codecs, processor cores, and so on.
> Now I that I have a handle on whats available and possible on most
> platforms I bought my first dev board a couple of days ago.  I can't
> wait for sun to open up there sparc cores.  So many ideas so little
> time!!
>
> I can't believe I went through my undergraduate education without
> trying fpga's out, and my focus on RF and optics was not very close to
> VLSI or control.  After 5 months though there are a ton of optics
> processing problems that can be sped up with fpgas.  Like I said, can't
> wait to start debugging!!
>
> So much to do, so little time...
> new Hobbyist
>

no need to wait for sun

commercial quality SPARC core and system on chip library is available now

http://www.gaisler.com

you need XC3S400 or larger (better larger) to implement a SPARC based system

-- 
Antti Lukats
http://www.xilant.com

> 
> Hmm, really? ;-) As far as I know the only "pure" hobbyists
> here are Antti and myself, the rest is more or less professional.
> 

There are many of us here who started out as pure hobbyists, but then 
grew our passion into a paying endeavor.  I started out in the mid '70's 
first with dissected radios, tape recorders etc, whatever I could get my 
hands on, with radio shack kits (many of which I heavily modified...one 
that comes to mind was a regulated power supply where the 2N3055 got hot 
enough to melt through the red plastic board/box that soon got a 
heatsink and a darlington pair for more output current and a switch to 
select output voltages).  From there, I started getting into logic. 
Between a 1976 Signetics IC databook (which is still on my bookshelf) 
and several of Lancaster's cookbooks (some of his circuits would never 
get past a critical review, but they were great for learning) I taught 
myself digital design.   Even built a couple of computers based on the 
then brand new 6800 (on an Ohio Scientific board), and then the Z-80 
scratch built on wire-wrap boards before graduating from high school in 
1979.

Like Philip said, I had a mentor (a friend of the family who is an EE 
and was consulting mostly in audio and telephony back in the 60's and 
70's) that gave me much of the motivation to make and improve on the 
projects in Radio Electronics (which I was subscribed to from 1971 to 
1982, I dumped the entire collection when it caused me to exceed my 
weight allowance in a move with the Air Force, Killed me, but I couldn't 
even give them away).

In article <slrndsgqr4.i5.weingart@irricana.cs.ualberta.ca>,
Tobias Weingartner <weingart@cs.ualberta.ca> wrote:
>Kevin Morris wrote:
>> 
>> Any takers?
>
>Real/Complete programming information would be a very good start to a new
>hobby phase.  But I think that all the FPGA vendors are too scared to give
>out this information.  Come on, xilinx, altera, etc, etc.  What could there
>possibly be so secret in the format for how to program your parts?  :)
>

Indeed.  I don't get it either.  How much can be reverse engineered from a 
bitstream format?  This closedness is a real hindrance to the development of 
an open source eco-system around FPGAs.

Any university open FPGA architectures being developed out there?  While it's 
probably too late in the game for a new FPGA company to enter the race, it's 
possible that one of the smaller, hungier players might be able to 
differentiate themselves by opening up their bitstream formats.

Phil

Nostalgia...
I built radios in high-school days, and was a ham operator during
college years. Later, in Sweden, I designed and built power supplies
and sold a hundred of them as a moonlight operation. Then the usual
audio amplifiers and speaker boxes.
Now the interest is rekindled and I play with the design of my
second-generation programmable clock module (1 Hz to 2.5 GHz with,
hopefully, 30 ps jitter). But this also taught me that, for top-notch
performance, you need the help of several friends and experts (software
design, pc-board lay-out, GHz trickery, test instrumentation) and of a
commercial manufacturer. We built a few hundred of the first generation
"X-Pod", and are using them inside the company on many test benches. So
it's more "skunk works" than hobby activity, but still the same fun.
I have toyed with the idea of a storage scope. The digital part in an
FPGA plus external RAM looks easy. But less than 500 MHz sample rate
seems to make it a toy, and at that rate the A/D becomes quite
expensive, and an input attenuator looks forbidding, But there are neat
examples of using the PC for display and control.
Peter Alfke, from home.

Peter Alfke wrote:
> Nostalgia...
> I built radios in high-school days, and was a ham operator during
> college years. Later, in Sweden, I designed and built power supplies
> and sold a hundred of them as a moonlight operation. Then the usual
> audio amplifiers and speaker boxes.
> Now the interest is rekindled and I play with the design of my
> second-generation programmable clock module (1 Hz to 2.5 GHz with,
> hopefully, 30 ps jitter). 

Digits of precision & granularity ?


But this also taught me that, for top-notch
> performance, you need the help of several friends and experts (software
> design, pc-board lay-out, GHz trickery, test instrumentation) and of a
> commercial manufacturer. 

A tad outside the average hobbiest resource pool ?

We built a few hundred of the first generation
> "X-Pod", and are using them inside the company on many test benches. So
> it's more "skunk works" than hobby activity, but still the same fun.
> I have toyed with the idea of a storage scope. The digital part in an
> FPGA plus external RAM looks easy. But less than 500 MHz sample rate
> seems to make it a toy, and at that rate the A/D becomes quite
> expensive, and an input attenuator looks forbidding, But there are neat
> examples of using the PC for display and control.

Yes, scopes are dominated by things other than the FPGA, so are not
ideal demo-examples.

My favourites would be for Xilinx to do a split
a) Freq Ctr & Signal Generator - Smallest/Cheapest FPGA version

b) Freq Ctr & Signal Generator - Money-no-object version

FreqCtr's can become quite complex - so a series of designs would show 
users more and more, but still have a HW platform that is
i)  FPGA dominated
ii) Clearly ahead of any uC alternative

-jg

Jim, beware, you are hitting a hot-button !
Jim Granville wrote:
>> Digits of precision & granularity ?
10 decimal digits fixed-point display, but 2 ppm accuracy.
Above 1 MHz limited by time base accuracy, below 1 MHz by display
(just because we are too lazy to make the display floating point...)
>
> > A tad outside the average hobbiest resource pool ?
I think so.
> >
> Yes, scopes are dominated by things other than the FPGA, so are not
> ideal demo-examples.
Yes and no. For low-performance, most complexity would be in FPGA,
DRAM, and PC.
>
> My favourites would be for Xilinx to do a split
> a) Freq Ctr & Signal Generator - Smallest/Cheapest FPGA version
Wait for the S3Eeval board. It includes a freq.gen design based on my
box. Ken Chapman did the control for both of them (PicoBlaze-based), so
you can be convinced it is good.
But it only goes to 80 MHz (?) and the jitter may be more than 100 ps,
since he has no PLL to clean it up further.
>
> b) Freq Ctr & Signal Generator - Money-no-object version
I am going for 2.5 GHz square wave, 1 Hz resolution, and lowest jitter.
But no arbitrary function, adjustable amplitude or duty cycle. All
those things are possible, but clutter up the design. Maybe there will
also come a USB-controlled derivative that offers more freedom.

Please tell me what people need a frequency counter for. I have thought
of a design for years, including reciprocal counting at low frequency
for high resolution with short capture time. But it died for lack of
interest. We could of course include something in the S3E eval board.
>
> FreqCtr's can become quite complex - so a series of designs would show
> users more and more, but still have a HW platform that is
> i)  FPGA dominated
> ii) Clearly ahead of any uC alternative
The S3E eval board accuracy will be limited by its 50 ppm xtal, and the
resolution might be pushed to almost 1 GHz. Display is no problem @ 2 x
16 digits.
A 20 times more accurate time base would cost <$20 extra.
I warned you, this is a hot button with me.
My thesis project, looong ago, was a frequency counter. It's deep in my
genes.
Peter

Peter Alfke wrote:
> Jim, beware, you are hitting a hot-button !
> Jim Granville wrote:
> 
>>>Digits of precision & granularity ?
> 
> 10 decimal digits fixed-point display, but 2 ppm accuracy.
> Above 1 MHz limited by time base accuracy, below 1 MHz by display
> (just because we are too lazy to make the display floating point...)
> 
>>>A tad outside the average hobbiest resource pool ?
> 
> I think so.
> 
>>Yes, scopes are dominated by things other than the FPGA, so are not
>>ideal demo-examples.
> 
> Yes and no. For low-performance, most complexity would be in FPGA,
> DRAM, and PC.
> 
>>My favourites would be for Xilinx to do a split
>>a) Freq Ctr & Signal Generator - Smallest/Cheapest FPGA version
> 
> Wait for the S3Eeval board. It includes a freq.gen design based on my
> box. Ken Chapman did the control for both of them (PicoBlaze-based), so
> you can be convinced it is good.
> But it only goes to 80 MHz (?) and the jitter may be more than 100 ps,
> since he has no PLL to clean it up further.
> 
>>b) Freq Ctr & Signal Generator - Money-no-object version
> 
> I am going for 2.5 GHz square wave, 1 Hz resolution, and lowest jitter.
> But no arbitrary function, adjustable amplitude or duty cycle. All
> those things are possible, but clutter up the design. Maybe there will
> also come a USB-controlled derivative that offers more freedom.

Those do sound like the Smallest/Cheapest and 'other end' I was
talking about.
Why stop at 1Hz ?


> Please tell me what people need a frequency counter for. I have thought
> of a design for years, including reciprocal counting at low frequency
> for high resolution with short capture time. But it died for lack of
> interest. We could of course include something in the S3E eval board.

When I say 'Freq Ctr' that is short hand for the higher end Freq Ctrs.
The better ones ( we use a venerable PM6672 here... ) can do
much besides simple frequency.

I'd start with the simplest gated counter designs, and then work up
to Reciprocal and Time-Interval counters, ..maybe Phase too.

A small nudge, and you can make a SigmaDelta ADC display section,
as that's really a % counter.

One idea I have, is for a Dual Readout Recip Counter :
A fast update readout, where the precision is the normal trade
off of update speed.
The second would accumulate precision, so the longer the probe
is held there, the more digits you get.

That gets a little tricky, as the whole system has to never drop
any edges.

Uses: As a software development tool, to verify correct settings.
Common errors are the off-by-one in divisiors etc.

Mostly 2 channel Time-interval, but also frequency.


> 
>>FreqCtr's can become quite complex - so a series of designs would show
>>users more and more, but still have a HW platform that is
>>i)  FPGA dominated
>>ii) Clearly ahead of any uC alternative
> 
> The S3E eval board accuracy will be limited by its 50 ppm xtal, and the
> resolution might be pushed to almost 1 GHz. Display is no problem @ 2 x
> 16 digits.
> A 20 times more accurate time base would cost <$20 extra.

That's fine. It should NOT be limited by the FPGA.
Users would be happy to add timebases as needed - yes, even to
atomic ones :)

For higher end examples, how about calibrate/correct via GPS timebase
(still using the low cost xtal)

That expands further, to give an absolute time reference - wider
audience, and with 2 lines, one could show 'human' time, and the other 
the snapshot of the 1 sec time pulse from the GPS, probably to
better than 5ns.

> I warned you, this is a hot button with me.
> My thesis project, looong ago, was a frequency counter. It's deep in my
> genes.

Talking of looong ago, I think my first film-processed project was a
compact 8 digit Freq Ctr, with many old fairchild part numbers.
That was before rubylith....

-jg

Jim Granville wrote:
> > Why stop at 1Hz ?
It is easy to go to mHz, just make the accumulator longer, but why?
With 1 ppm absolute accuracy, even the Hz is dubious above 1 MHz.
Who is interested in frequencies below 1 MHz? That also goes for the
counter.

Jim, you seem to overestimate the time and energy we here can expend on
sophisticated and increasingly specialized appliations. That's why I
stay with a basic, but extreme design that gives us some real
usefulness and also some bragging rights.

There are always more urgent projects breathing down our necks:
Verifying, testing, finding problems and work-arounds, write
documentation, plan the next generation, prove SEU hardness, deal with
unhappy postings on the newsgroup, give seminars, attend conferences,
analyze the features and find the shortcomings of the "other guy",
support Markeing, but prevent them from exaggerating...
Life is never dull, often challenging, and rarely really frustrating.
Peter Alfke

>So, I wonder, how many people here are exclusively logic designers,
>and how many are more general EEs, who deal with the analog, power,
>thermal, and other aspects of electronic design?

I've never worked with any "exclusively logic designers".  (At
least I don't think I have.  Maybe one snuck in that I didn't
notice.)

There is also the other end of the spectrum: firmware/drivers/software.
For most projects that I've worked on, that's a cricital
part of the big picture.

You could also expend up to system architecture and stuff like that.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.

"Phil Tomson" <ptkwt@aracnet.com> schrieb im Newsbeitrag 
news:dqefe401nol@enews4.newsguy.com...
> In article <slrndsgqr4.i5.weingart@irricana.cs.ualberta.ca>,
> Tobias Weingartner <weingart@cs.ualberta.ca> wrote:
>>Kevin Morris wrote:
>>>
>>> Any takers?
>>
>>Real/Complete programming information would be a very good start to a new
>>hobby phase.  But I think that all the FPGA vendors are too scared to give
>>out this information.  Come on, xilinx, altera, etc, etc.  What could 
>>there
>>possibly be so secret in the format for how to program your parts?  :)
>>
>
> Indeed.  I don't get it either.  How much can be reverse engineered from a
> bitstream format?  This closedness is a real hindrance to the development 
> of
> an open source eco-system around FPGAs.
>
> Any university open FPGA architectures being developed out there?  While 
> it's
> probably too late in the game for a new FPGA company to enter the race, 
> it's
> possible that one of the smaller, hungier players might be able to
> differentiate themselves by opening up their bitstream formats.
>
> Phil

Phil, Atmel AT40K/AT94K bitstream format is almost open
eg it is available under NDA from Atmel, and open source reverse engineered
documentation is also available - no NDA :)

As of BIG FPGA companies making their bitstream format public - do not hope!

because the bitstream holds not only the 'known' bits like routing and LUT, 
but
also factory stuff

bits that compensate against technology changes, those are 'figured out' by
actual measurement by the FPGA companies AFTER wafers are manufactured
that is the FPGA companies makes their chips to have a little 'fine tuning' 
to
be done, this fixing is done by bitgen and is totally invisible for the 
normal user.

second there are factory test bits and settings, again something that the 
end
user should not mess up

there are some hidden FPGA primitives that are partially visible for the
end user but not useable by end user, like PMV primitive in V4 and S3

there are probably hidden features and primitives that are totally invisble
for the end user as well.

so there are reasons for keeping the bitstream non public.

for Xilinx and Lattice the main bitstream info is in NeoCad "BFD" files,
those are simple ordered lists of bit names, bitgen uses that
 info to convert an NCD to bitstream

NCD file is almost 1:1 the same as the XDL file would be so actually
pretty much of the bit info is visible for those who want to see

-- 
Antti Lukats
http://www.xilant.com