LVDS Input buffer in VHDL (ISE)

I'm trying to instantiate some LVDS input buffers in VHDL using the 
following code:

  LVDS_lines:
    for i in 0 to 19 generate
      Inputs_LVDS : IBUFDS_LVDS_25_DT     -- LVDS input buffer with Rterm 
active
        port map (
          I => data_lvds_in_p(i),
          IB => data_lvds_in_n(i),
    O => data_lvds_in_sig(i));
  end generate;


but ISE doesn't seem to recognise IBUFDS_LVDS_25_DT as it just gives me an 
Undefined Symbol error. Missing off the DT is OK but I need the termination 
resistor to be active so it has to be this buffer.

If anyone has any ideas what's wrong I'd be grateful to hear.

TIA.

Rog. 

Roger <enquiries@rwconcepts.co.uk> wrote:
> I'm trying to instantiate some LVDS input buffers in VHDL using the 
> following code:

>   LVDS_lines:
>     for i in 0 to 19 generate
>       Inputs_LVDS : IBUFDS_LVDS_25_DT     -- LVDS input buffer with Rterm 
> active
>         port map (
>           I => data_lvds_in_p(i),
>           IB => data_lvds_in_n(i),
>     O => data_lvds_in_sig(i));
>   end generate;


> but ISE doesn't seem to recognise IBUFDS_LVDS_25_DT as it just gives me an 
> Undefined Symbol error. Missing off the DT is OK but I need the termination 
> resistor to be active so it has to be this buffer.

I also started to coding LVDS buffers, but for verilog. 
module xxx ( input gclk_p, input gclk_n);
	wire gclk;
   	IBUFGDS ibuf1(.O(gclk),.I(gclk_p),.IB(gclk_n));
endmodule
selected automatically the desired LVDS_25 (from the .map file):
P76|gclk_p|DIFFM|IO_L32P_5/GCLK2|INPUT|LVDS_25|5||||NONE||LOCATED||NO|NONE|
P77|gclk_n|DIFFS|IO_L32N_5/GCLK3|INPUT|LVDS_25|5||||NONE||LOCATED||NO|NONE|

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Is this Virtex-4?

Roger wrote:
> I'm trying to instantiate some LVDS input buffers in VHDL using the 
> following code:
> 
>   LVDS_lines:
>     for i in 0 to 19 generate
>       Inputs_LVDS : IBUFDS_LVDS_25_DT     -- LVDS input buffer with Rterm 
> active
>         port map (
>           I => data_lvds_in_p(i),
>           IB => data_lvds_in_n(i),
>     O => data_lvds_in_sig(i));
>   end generate;
> 
> 
> but ISE doesn't seem to recognise IBUFDS_LVDS_25_DT as it just gives me an 
> Undefined Symbol error. Missing off the DT is OK but I need the termination 
> resistor to be active so it has to be this buffer.

You didn't mention what part you are using. But generally, Xilinx refers 
to it's termination scheme as "Digitally Controlled Impedance" IIRC, and 
the IO name is IBUFDS_LVDS_25_DCI.

The part is Virtex IIPro. It's not the DCI I'm looking for, it's the on-chip 
100R termination.

Thanks.

Roger.


"Roger" <enquiries@rwconcepts.co.uk> wrote in message 
news:T0dBf.108165$7p5.45109@newsfe4-win.ntli.net...
> I'm trying to instantiate some LVDS input buffers in VHDL using the 
> following code:
>
>  LVDS_lines:
>    for i in 0 to 19 generate
>      Inputs_LVDS : IBUFDS_LVDS_25_DT     -- LVDS input buffer with Rterm 
> active
>        port map (
>          I => data_lvds_in_p(i),
>          IB => data_lvds_in_n(i),
>    O => data_lvds_in_sig(i));
>  end generate;
>
>
> but ISE doesn't seem to recognise IBUFDS_LVDS_25_DT as it just gives me an 
> Undefined Symbol error. Missing off the DT is OK but I need the 
> termination resistor to be active so it has to be this buffer.
>
> If anyone has any ideas what's wrong I'd be grateful to hear.
>
> TIA.
>
> Rog.
> 

Roger wrote:
> The part is Virtex IIPro. It's not the DCI I'm looking for, it's the on-chip
> 100R termination.
>
What version of ISE?

Are you using the unisim library like this:
 library unisim;
   use unisim.vcomponents.all;

Or, defining the component yourself?

Instead of using the named suffix I/O buffer, try sticking an
IO_STANDARD of LVDS_25_DT on an input buffer of type IBUF{G}DS

See also Answer Record 17244

Brian

Brian,

Thanks, this was really useful.

I'm using version 7.1 of ISE and yes, I have the unisim library lines in the 
code.

I used the generic ... IOSTANDARD = LVDS_25_DT on an IBUFDS as you suggested 
and it worked! I don't know why and probably never will but it allows me to 
progress with the design now. Thanks again.

Roger.

"Brian Davis" <brimdavis@aol.com> wrote in message 
news:1138073412.403694.257500@o13g2000cwo.googlegroups.com...
> Roger wrote:
>> The part is Virtex IIPro. It's not the DCI I'm looking for, it's the 
>> on-chip
>> 100R termination.
>>
> What version of ISE?
>
> Are you using the unisim library like this:
> library unisim;
>   use unisim.vcomponents.all;
>
> Or, defining the component yourself?
>
> Instead of using the named suffix I/O buffer, try sticking an
> IO_STANDARD of LVDS_25_DT on an input buffer of type IBUF{G}DS
>
> See also Answer Record 17244
>
> Brian
> 

I had the same issue. The IBUFDS_LVDS_25_DT is shown in the library package 
but XST doesn't recognize it. I ended up doing what you did.
Chuck


"Roger" <enquiries@rwconcepts.co.uk> wrote in message 
news:nLxBf.109663$7p5.53403@newsfe4-win.ntli.net...
> Brian,
>
> Thanks, this was really useful.
>
> I'm using version 7.1 of ISE and yes, I have the unisim library lines in 
> the code.
>
> I used the generic ... IOSTANDARD = LVDS_25_DT on an IBUFDS as you 
> suggested and it worked! I don't know why and probably never will but it 
> allows me to progress with the design now. Thanks again.
>
> Roger.
>

Roger wrote:
>
> Thanks, this was really useful.
>
 Glad that worked.

> I'm using version 7.1 of ISE

 And, now I know what to change when I switch to 7.1 !

 I haven't updated from 6.3 yet at home to create a test case,
but I've had problems with attributes not sticking to diff. buffers
before ( especially the _DIFF_OUT variants )

>
> I don't know why and probably never will but it allows me to
> progress with the design now.
>
 I think Xilinx is getting away from the named suffixes for the
newer families, so perhaps they broke something in the tool flow.

Brian

Thanks everyone. This has been useful for me and others.

Roger.

"Brian Davis" <brimdavis@aol.com> wrote in message 
news:1138160016.066348.150980@f14g2000cwb.googlegroups.com...
> Roger wrote:
>>
>> Thanks, this was really useful.
>>
> Glad that worked.
>
>> I'm using version 7.1 of ISE
>
> And, now I know what to change when I switch to 7.1 !
>
> I haven't updated from 6.3 yet at home to create a test case,
> but I've had problems with attributes not sticking to diff. buffers
> before ( especially the _DIFF_OUT variants )
>
>>
>> I don't know why and probably never will but it allows me to
>> progress with the design now.
>>
> I think Xilinx is getting away from the named suffixes for the
> newer families, so perhaps they broke something in the tool flow.
>
> Brian
>