help:dual-edge flip-flop possible using Verilog?

Im designing a module working as an fm0-encoder, the clk and max
datarate of which are both 640KHz. It is not complicated when the
datarate is lower than 320K, the half of clk. But when the datarate of
640K, the clk frequency, is concerned, the problem comes that I have to
change the state at both the rising and falling edge of the clk. Now I
am using a mothod via combinational output, which is not so good and
expansible as registered output using an FSM. I think that an FSM using
DET(dual-edge flip-flop) would work, but I am not sure wether it is
recommandable to use det and I don't know how to describe a det using
synthesizable Verilog?
It would be appreciated very much if some of you can
*comments about the det method,
*the methed about how to describe a det flip-flop

thans a lot for any help!

yyqonline schrieb:
> Im designing a module working as an fm0-encoder, the clk and max
> datarate of which are both 640KHz. It is not complicated when the
> datarate is lower than 320K, the half of clk. But when the datarate of
> 640K, the clk frequency, is concerned, the problem comes that I have to
> change the state at both the rising and falling edge of the clk. Now I
> am using a mothod via combinational output, which is not so good and
> expansible as registered output using an FSM. I think that an FSM using
> DET(dual-edge flip-flop) would work, but I am not sure wether it is
> recommandable to use det and I don't know how to describe a det using
> synthesizable Verilog?
> It would be appreciated very much if some of you can
> *comments about the det method,
> *the methed about how to describe a det flip-flop
> 
> thans a lot for any help!

It is not difficult to driscrobe dual-edge flip-flop in an HDL.
The real question is: Can you build them in your target technology?
Most FPGAs do not have them and most standard cell libraries do not
have them either.

Kolja Sulimma

yyqonline wrote:
> Im designing a module working as an fm0-encoder, the clk and max
> datarate of which are both 640KHz. It is not complicated when the
> datarate is lower than 320K, the half of clk. But when the datarate of
> 640K, the clk frequency, is concerned, the problem comes that I have to
> change the state at both the rising and falling edge of the clk. Now I
> am using a mothod via combinational output, which is not so good and
> expansible as registered output using an FSM. I think that an FSM using
> DET(dual-edge flip-flop) would work, but I am not sure wether it is
> recommandable to use det and I don't know how to describe a det using
> synthesizable Verilog?
> It would be appreciated very much if some of you can
> *comments about the det method,
> *the methed about how to describe a det flip-flop
>
> thans a lot for any help!

Do you really mean KHz and not MHz?  If this is not a typo I would
suggest using a much faster clock to run an FSM that samples the
640KHz clock and uses edge detection (XOR on two stages of
flip-flop) to enable data transfer.

If you're really talking MHz, modern FPGA's have ways to deal with this
at the I/O buffer (double-data-rate flip-flops).

Generally multi-edge flip-flops are not synthesizable, but if the part
has them, they can be instantiated.  i.e. you can't just write:

always @ (posedge clk or negedge clk)
 ...

and expect the synthesis tool to generate useful RTL.

I think the only device that supports this are the Xilinx CoolRunner II.

This Should work:

always @(posedge Clk or negedge Clk)
begin
	if(Rst == 1)
		Cnt <=0;
	else
		Cnt <= Cnt +1;

end

yyqonline wrote:
> Im designing a module working as an fm0-encoder, the clk and max
> datarate of which are both 640KHz. It is not complicated when the
> datarate is lower than 320K, the half of clk. But when the datarate of
> 640K, the clk frequency, is concerned, the problem comes that I have to
> change the state at both the rising and falling edge of the clk. Now I
> am using a mothod via combinational output, which is not so good and
> expansible as registered output using an FSM. I think that an FSM using
> DET(dual-edge flip-flop) would work, but I am not sure wether it is
> recommandable to use det and I don't know how to describe a det using
> synthesizable Verilog?
> It would be appreciated very much if some of you can
> *comments about the det method,
> *the methed about how to describe a det flip-flop
> 
> thans a lot for any help!
> 

I suggest we wait for the original poster to clarify.
I think there is no real need for a dual-edge triggered flip-flop.
Definitely not at the low frequenciesmentioned.
There is also a simple circuit that XOR differentiates the clock, thus
generating a clock pulse at both the rising and the falling edge. (See,
among others, at "Six Easy Pieces" in TechXclusives)
Peter Alfke

\quote
Do you really mean KHz and not MHz?  If this is not a typo I would
suggest using a much faster clock to run an FSM that samples the
640KHz clock and uses edge detection (XOR on two stages of
flip-flop) to enable data transfer.
If you're really talking MHz, modern FPGA's have ways to deal with this

at the I/O buffer (double-data-rate flip-flops).
Generally multi-edge flip-flops are not synthesizable, but if the part
has them, they can be instantiated.  i.e. you can't just write:
always @ (posedge clk or negedge clk)
 ...
and expect the synthesis tool to generate useful RTL.
\quote

Now we are using FPGA for verification while at the end this circuit
will be implemented by asic tech, so the system clock is fixed at
640Khz.
I am not sure whether
always @(posedge clk or negedge clk)
is synthesizable.

Thanks a lot for replying.
\quote
There is also a simple circuit that XOR differentiates the clock, thus
generating a clock pulse at both the rising and the falling edge. (See,

among others, at "Six Easy Pieces" in TechXclusives)
\quote
I have found the circuit and thanks for information.
I am checking the stability of this circuit.
If this circuit is reliable, I think this may be a good idea.

The circuit is reliable, although the generated pulse width is
determined by gate delays. But it is self-compensating, since the clock
pulse will not end until the flip-flop has toggled. It's kind of
clever, if I am allowed to say so...
Peter Alfke

The circuit is reliable, although the generated pulse width is
determined by gate delays. But it is self-compensating, since the clock
pulse will not end until the flip-flop has toggled. It's kind of
clever, if I am allowed to say so...
Peter Alfke

Peter Alfke wrote:
> The circuit is reliable, although the generated pulse width is
> determined by gate delays. But it is self-compensating, since the clock
> pulse will not end until the flip-flop has toggled. 

It probably needs some care, to ensure CLK_min times are ok ?

eg if you drive a large clock tree, it would be better to not
use a local FF clk, and then buffer, but to buffer, and then
FF.CLK from the CLK tree output, with optional additional
delays, if you want even more margin.

> It's kind of clever, if I am allowed to say so...
  Yes, I recall a similar [XOR-Q] clock scheme many, many years ago, on
a circuit ( from HP?) for Biphase decode.

-jg