Back to max thermal and power for XC4VLX200's

So, back to the question of worst case designs for supporting RC.

What are the worst case VccInt currents that various packages will
handle?  How does that relate to what is necessary for balancing the
design across multi phase clocks to spread the current spikes following
clock edges in time?

Is there any means to get a handle on the current time spread profile
by knowing the distribution of routing lengths and logic depths for
each clock?

I assume ground pads are shared between VccInt and I/O? If so, how
would one combine worst case VccInt ground currents with the worst case
I/O ground switching currents for a worst case package level design
spec?

<fpga_toys@yahoo.com> wrote in message 
news:1138753558.833731.142700@g14g2000cwa.googlegroups.com...
> So, back to the question of worst case designs for supporting RC.
>
> What are the worst case VccInt currents that various packages will
> handle?
>
Hi John,
OK, let's work through this. First I'll pick a package, say FG672. Now, I'll 
choose a part, say FX20.
From UG075 ThetaC =  0.4 and ThetaB = 3.8. So, best case thermal resistance 
from junction to case = 0.4 // 3.8 = 0.36 K/W

OK, say we've selected a commercial grade part. That means our junction 
temperature can't exceed 85degC or 358K (from DS112). The minimum Vccint 
voltage is 1.14V (from DS302).

Right, you asked for worst case Vccint current, which I assume means 'what's 
the maximum current' the package can handle.

Assuming best case heatsinking, we can keep the case at c.0K with a perfect 
liquid Helium cooled heatsink. Therefore we can dissapate 358/0.36 = 1000W. 
Vccint can be 1.14V, so that's a maximum current of about 870A.

Now do you see why you're asking the wrong question? ;-) Of course my 
example is a ridululous exaggeration, but your posting provided little to go 
on. You need to do a proper analysis with thermal simulation tools to get a 
meaningful answer, and even when you get that answer it'll be wrong!

Try this bloke's book:-
http://tkordyban.coolingzone.com/
There's a brief review of the book by an FPGA expert on Cambrian Design's 
website
http://www.sonic.net/~bobperl/blogger/2006/01/book-of-month-hot-air-rises-and-heat.html

HTH, Syms.

p.s. I hereby release the copyright on this post to avoid any legal 
ramifications. ;-)

"Symon" <symon_brewer@hotmail.com> wrote in message 
news:43e07882$0$15785$14726298@news.sunsite.dk...
>
> Now do you see why you're asking the wrong question? ;-) Of course my 
> example is a ridululous exaggeration, but your posting provided little to 
> go >
I sound like Donna Chang out of Seinfeld. Of course it should be 
'ridicurous'. I need coffee.
Cheers, Syms. 

fpga_toys@yahoo.com wrote:
> So, back to the question of worst case designs for supporting RC.
> 
> What are the worst case VccInt currents that various packages will
> handle?  How does that relate to what is necessary for balancing the
> design across multi phase clocks to spread the current spikes following
> clock edges in time?

You won't be limited by the current carrying capabilities of the wires. 
  It's the thermal that will limit you.  Flip-chip packages can deal 
with a lot more heat and they can deal with a lot more current.  You're 
probably concerned about the wire bond packages but those have higher 
thermal resistance, limiting the amount of power.

> Is there any means to get a handle on the current time spread profile
> by knowing the distribution of routing lengths and logic depths for
> each clock?

To keep working under high speed *or* low speed conditions, the current 
effects from a single clock edges *must* be mitigated in the first few 
hundred picoseconds by distributed capacitance on the FPGA silicon and 
package.  The "high frequency" capacitance needed externally is 
typically for the Gigahertz and below frequency range.  The nice thing 
here is that the huge super-short current spikes don't need much 
capacitance to keep the voltage up.  Proper decoupling needs an 
understanding of what the biggest current steps are in the applicable 
frequency range.  We don't need to know the current "surge" at each 
clock edge in these devices; the worst case condition for this worry of 
yours is one single clock distributed across the chip.  Single clock 
synchronous designs make up a large number of FPGA designs.  There 
aren't problems.  It's when you go from nearly no activity to massive 
activity (or back) that the external decoupling and power regulation 
needs to handle the massive change in current.  This is design.

> I assume ground pads are shared between VccInt and I/O? If so, how
> would one combine worst case VccInt ground currents with the worst case
> I/O ground switching currents for a worst case package level design
> spec?

Again, stop thinking that the wires will cause you problems.  Your balls 
won't vaporize and your wires bonds won't fuse because the quantity and 
distribution of power in the FPGAs accommodates some nasty design 
corners.  If you can remove the heat, you can source the current.  If 
this wasn't the case there would be a significantly larger population 
than you freaking over the power.


Symon was going over some thermal resistance values in another response. 
  It's that level of engineering needed for proper heat sing desing.  I 
did a quick look at the Aavid embedded fan heat sink for a XIlinx part 
when you were first blowing the design issues out of proportion.  The 
junction-to-case, thermal interface material, and heat sink had thermal 
resistance values of 0.1 C/W, 0.2 C/W, and 1.38C/W (I think that's 
"respectively").  If you were designing for 40W in 45C ambient with 125C 
die temperature, everything's fine with that simple "active" heat sink. 
  The 125C is the temperature you mentioned in an earlier post but the 
commercial and industrial *operating* die temps are lower than the 
"absolute maximum" junction temperature value you referenced, at 85C and 
100C for the Virtex-4 series, respectively.  See the ordering 
information for the junction temperature ranges.

So in the example above you'd need a better solution than that 
convenient small embedded-fan heat sink.  The processor heat sinks 
demonstrate thermal resistance values far below the 1.38C/W for this one 
heat sink.  Proper selection - or design - of the heat sinks are 
required to meet your maximum operating power and maximum operating 
ambient temperature.

"John_H" <johnhandwork@mail.com> wrote in message 
news:__3Ef.16063$oo1.12158@trnddc02...
> fpga_toys@yahoo.com wrote:
>> So, back to the question of worst case designs for supporting RC.
>>
>> What are the worst case VccInt currents that various packages will
>> handle?  How does that relate to what is necessary for balancing the
>> design across multi phase clocks to spread the current spikes following
>> clock edges in time?
>
> You won't be limited by the current carrying capabilities of the wires. 
> It's the thermal that will limit you.  Flip-chip packages can deal with a 
> lot more heat and they can deal with a lot more current.  You're probably 
> concerned about the wire bond packages but those have higher thermal 
> resistance, limiting the amount of power.
>
Hi John,
Indeed! I didn't even consider the OP meant the current carrying 
capabilities of the wires when I replied.
Cheers, Syms.

p.s. I'm glad my "balls won't vaporize"! :-) 

Symon wrote:
> Assuming best case heatsinking, we can keep the case at c.0K with a perfect
> liquid Helium cooled heatsink. Therefore we can dissapate 358/0.36 = 1000W.
> Vccint can be 1.14V, so that's a maximum current of about 870A.
>
> Now do you see why you're asking the wrong question? ;-) Of course my
> example is a ridululous exaggeration, but your posting provided little to go
> on. You need to do a proper analysis with thermal simulation tools to get a
> meaningful answer, and even when you get that answer it'll be wrong!

If we were talking about mounting bare die to my pcb your answer would
be
close.

Now, what is the voltage drop from my pcb pads to the die at 870A for
both the
ground and VccInt paths?

Those little tiny balls, via's and traces on the chip carrier PCB have
just enough
cross sectional area to be called fuses. And not enough cross sectional
area to
avoid a voltage drop.

<fpga_toys@yahoo.com> wrote in message 
news:1138808303.733536.253170@g44g2000cwa.googlegroups.com...
>
> Now, what is the voltage drop from my pcb pads to the die at 870A for
> both the
> ground and VccInt paths?
>
> Those little tiny balls, via's and traces on the chip carrier PCB have
> just enough
> cross sectional area to be called fuses. And not enough cross sectional
> area to
> avoid a voltage drop.
>
You're forgetting that the liquid helium cooling we've designed in has made 
your tiny balls into super-conductors. Both Lead and Tin are Type 1 
superconductors. (Not sure about the solder alloy though, maybe you need 
RoHS parts?) You now only need to find the current that causes the critical 
magnetic field strength above which the superconductivity stops.
Sadly, gold and copper don't superconduct; their lattice vibrations are too 
small. (Hint :- Think Cooper pairs.) However, the liquid helium should stop 
them vaporizing. All we need to do is turn up the external Vccint a little 
to compensate for the voltage drop in the traces and bond wires thus keeping 
the Vccint on the die in spec.
:-)
See how crazy this gets without enough data to work on?
Cheers, Syms. 

Symon wrote:
> You're forgetting that the liquid helium cooling we've designed in has made
> your tiny balls into super-conductors. Both Lead and Tin are Type 1
> superconductors. (Not sure about the solder alloy though, maybe you need
> RoHS parts?) You now only need to find the current that causes the critical
> magnetic field strength above which the superconductivity stops.
> Sadly, gold and copper don't superconduct; their lattice vibrations are too
> small. (Hint :- Think Cooper pairs.) However, the liquid helium should stop
> them vaporizing. All we need to do is turn up the external Vccint a little
> to compensate for the voltage drop in the traces and bond wires thus keeping
> the Vccint on the die in spec.
> :-)
> See how crazy this gets without enough data to work on?
> Cheers, Syms.

No, only the heat spreader is at 0K, the die is at max temp, and the
FR-4 to my pcb would have to assume chip temp less free air heat
losses.

Shall we review your calcs assuming the die was at commerical temp
limits?

fpga_toys@yahoo.com wrote:
> Symon wrote:
> > See how crazy this gets without enough data to work on?
> > Cheers, Syms.
>
> No, only the heat spreader is at 0K, the die is at max temp, and the
> FR-4 to my pcb would have to assume chip temp less free air heat
> losses.
>
> Shall we review your calcs assuming the die was at commerical temp
> limits

See how crazy this gets without enough data to work on?

You do not have a clue what the voltage drop between the host pcb and
the die is at any current, much less your 870A example.

Show me in the data sheet please :)

<fpga_toys@yahoo.com> wrote in message 
news:1138813669.939309.62810@g47g2000cwa.googlegroups.com...
>
>
> No, only the heat spreader is at 0K, the die is at max temp, and the
> FR-4 to my pcb would have to assume chip temp less free air heat
> losses.
>
But the Helium is superfluid so we can make it flow past the balls between 
the package and the FR4 with no viscous drag. Tiny balls at near 0K. OK?
:-)
Syms.

p.s. For commercial temperature rated parts the current rating goes up by a 
factor of (125 + 273.13) / (85 + 273.13) . I guess.