Back to max thermal and power for XC4VLX200's

Symon wrote:

> But the Helium is superfluid so we can make it flow past the balls between
> the package and the FR4 with no viscous drag. Tiny balls at near 0K. OK?
> :-)

No the tiny balls are the dia attach to the carrier FR4 pcb to convert
the
die pad pitch to the external ball array pitch.

So you have heat spreader on one side, sealed die ball attached to FR-4
carrier, thru vias and traces to the external ball array for customer
attach.

The FR-4 and via's have significantly higher thermal resistance than
the
heat spreader side.

That aside .. probably violates the storage and operating temp range
for
the part.

Anyway, the point is that everyone assumes the designs are thermally
limited, which given the xtreme case of He cooling may not be the case.

The limit after that is the voltage drop between customer attach balls
and
the die for both ground and VccInt paths, which is not spec'd

On 1 Feb 2006 10:01:47 -0800, fpga_toys@yahoo.com wrote:

>The limit after that is the voltage drop between customer attach balls
>and
>the die for both ground and VccInt paths, which is not spec'd

Is it difficult to measure typical values of the voltage drop on
actual hardware though?  Just set some outputs to be CMOS highs and
lows and measure their voltage at some convenient spot on the board.

I can't remember the IBIS curves, but I think the CMOS outputs do pull
all the way to the rail if the current is low enough.

Regards,
Allan

Allan Herriman wrote:
> Is it difficult to measure typical values of the voltage drop on
> actual hardware though?  Just set some outputs to be CMOS highs and
> lows and measure their voltage at some convenient spot on the board.

Measuring VccInt from an I/O pad?   ... some trick?

<fpga_toys@yahoo.com> wrote in message 
news:1138820483.937142.234800@g43g2000cwa.googlegroups.com...
>
> Allan Herriman wrote:
>> Is it difficult to measure typical values of the voltage drop on
>> actual hardware though?  Just set some outputs to be CMOS highs and
>> lows and measure their voltage at some convenient spot on the board.
>
> Measuring VccInt from an I/O pad?   ... some trick?
>
Leave one Vccint ball and one Gnd ball on the FG package disconnected. Use 
those signals as the feedback circuit of your power supply so that the PSU 
servos the on die voltage to the correct value.
Cheers, Syms.
p.s. Sorry for getting your tiny balls mixed up with the package balls 
earlier. I was plumb lead astray. 

Symon wrote:
> Leave one Vccint ball and one Gnd ball on the FG package disconnected. Use
> those signals as the feedback circuit of your power supply so that the PSU
> servos the on die voltage to the correct value.

Interesting idea. Would help to know a lot more about the power and
ground
busses on the chip.

If there was some significant on chip capacitance for the VccInt power
rails
that would be tempting. It would take some careful design to keep that
servo
loop stable given the extremely short transient nature of the power
use.

> Cheers, Syms.
> p.s. Sorry for getting your tiny balls mixed up with the package balls
> earlier. I was plumb lead astray.

hehehe ... was fun anyway :)

When the packaging guide thermal discussion talks about "high end"
being 25W, and you are considing a worst case design that might be
several times that you really have to wonder what the real design
considerations are at this fringe. There clearly isn't enough data up
front to do a pencil and paper design, and still feel good about it.

Symon wrote:

> <fpga_toys@yahoo.com> wrote in message 
> news:1138820483.937142.234800@g43g2000cwa.googlegroups.com...
> 
>>Allan Herriman wrote:
>>
>>>Is it difficult to measure typical values of the voltage drop on
>>>actual hardware though?  Just set some outputs to be CMOS highs and
>>>lows and measure their voltage at some convenient spot on the board.
>>
>>Measuring VccInt from an I/O pad?   ... some trick?
>>
> 
> Leave one Vccint ball and one Gnd ball on the FG package disconnected. Use 
> those signals as the feedback circuit of your power supply so that the PSU 
> servos the on die voltage to the correct value.

  That does sound like a good idea, you probably should probe a package 
first, to verify the metalization lattice, and so choose a 
'representative' pair - also ones that have reasonable adjacent density, 
so they will not be missed....

  Then, you can locally power each FPGA, and I'd also add a thermal 
sensor on the PCB rear, just to double check what the die thermal diodes 
are telling you.

  I'd also route an IO pin, to the 'Smart PSU', that outputs a divided 
ring oscillator, so you can also track an actual freq-capable point.
[ you _will_ want to overclock this, sometimes :) ]

  Each FPGA can then be Vcc adjusted, and even Clock adjusted, and the 
FAN (or pumps) cranked up accordingly...

-jg

All,

More heat is conducted out the bumps, through the substrate, through to 
the pcb than through the backside heat spreader (without a heatsink).

Even with a heatsink, as much as half of the power is going through to 
the pcb.

I know that is hard to believe, but the heat is much closer to the 
bumps, the bumps are metal (ultra low alpha lead), and they go directly 
to a copper plane in the substrate (package pcb).  FR4 and epoxies are 
pretty good at conducting heat.

The lead balls to the copper pcb completes the (best) heat conduction path.

The backside of the die is almost 1 mm of SiO2 away from the area that 
is hot, and has to then go through a thermal compound to get to the top 
heat spreader, and then has to be mechanically bonded to a heatsink (if 
you really want to get power out of the top of the package).

Or so I am lead to believe.

(I love the puns in this thread).

Austin



Jim Granville wrote:

> Symon wrote:
> 
>> <fpga_toys@yahoo.com> wrote in message 
>> news:1138820483.937142.234800@g43g2000cwa.googlegroups.com...
>>
>>> Allan Herriman wrote:
>>>
>>>> Is it difficult to measure typical values of the voltage drop on
>>>> actual hardware though?  Just set some outputs to be CMOS highs and
>>>> lows and measure their voltage at some convenient spot on the board.
>>>
>>>
>>> Measuring VccInt from an I/O pad?   ... some trick?
>>>
>>
>> Leave one Vccint ball and one Gnd ball on the FG package disconnected. 
>> Use those signals as the feedback circuit of your power supply so that 
>> the PSU servos the on die voltage to the correct value.
> 
> 
>  That does sound like a good idea, you probably should probe a package 
> first, to verify the metalization lattice, and so choose a 
> 'representative' pair - also ones that have reasonable adjacent density, 
> so they will not be missed....
> 
>  Then, you can locally power each FPGA, and I'd also add a thermal 
> sensor on the PCB rear, just to double check what the die thermal diodes 
> are telling you.
> 
>  I'd also route an IO pin, to the 'Smart PSU', that outputs a divided 
> ring oscillator, so you can also track an actual freq-capable point.
> [ you _will_ want to overclock this, sometimes :) ]
> 
>  Each FPGA can then be Vcc adjusted, and even Clock adjusted, and the 
> FAN (or pumps) cranked up accordingly...
> 
> -jg
> 

Jim Granville wrote:
>   Each FPGA can then be Vcc adjusted, and even Clock adjusted, and the
> FAN (or pumps) cranked up accordingly...

Still begs the question of where the fuse point is for the package. A
140 VccInt 6 mil 1/2oz traces aren't exactly rated for any serious
current without fusing. The solder balls to the die don't have great
cross sections either. Plating boundries at the via junctions don't
help, as the effective cross section for worst case design lowers due
to etching and plating variances.

This would leave the VccInt limit for the package something in the area
of 15-25A using std tables and assuming a lot about the carrier pcb -
or about 18-30W. Probably a LOT less as this isn't free air and one
side is up against the hot die under worst case load, and the other
side is insulated with the host PCB FR-4 providing little cooling for
the IR heating in the traces/vias.

Clearly a dense RC design at modest frequencies can easily exceed this
in dynamic power.

It's hard to even get a ball park without solid design data for the
package pcb carrier board.

There are additional questions which rapidly pop up, like can the die
metalization (probably aluminum) even handle these currents without
heating and migration problems.

So, lacking real data from Xilinx ... it's probably very fair to say
that the UG075 statement showing the high end limit at 25W may well be
the limit for power when VccInt and VccIO are combined. The lack of
real data really hampers designing safe worst case RC applications.

If this is the case, then RC designs can not use any serious fraction
of the raw performance in terms of "gate/LUT count" times "clock rate"
product you might assume from the data sheet.

Jim Granville wrote:
>   I'd also route an IO pin, to the 'Smart PSU', that outputs a divided
> ring oscillator, so you can also track an actual freq-capable point.
> [ you _will_ want to overclock this, sometimes :) ]

I've been a little gun shy of leaving several fast ring oscillators
running on Virtex parts since taking out two consecutive XCV800's that
way a couple years ago, my lab desktop board after a client returned a
dead board having done the same. It wasn't even that warm at the heat
sink. I've never been sure if that was just a freak, or something to
worry about.

I asked the local FAE about it last year when doing the first XC4VLX200
design and kinda got a shrug and strange look of disbelief. After that
I've been more careful to keep toggle rates closer to the chip's stated
max clock rate.

fpga_toys@yahoo.com wrote:
> Jim Granville wrote:
> 
>>  Each FPGA can then be Vcc adjusted, and even Clock adjusted, and the
>>FAN (or pumps) cranked up accordingly...
> 
> 
> Still begs the question of where the fuse point is for the package. A
> 140 VccInt 6 mil 1/2oz traces aren't exactly rated for any serious
> current without fusing.

But you would not use 6 mil, 1.2 oz traces, in something you KNEW was
going to the corners, would you ?
Via escapes can be much wider than that, and you can always add multiple
thermal vias, to your PCB...

  The solder balls to the die don't have great
> cross sections either. Plating boundries at the via junctions don't
> help, as the effective cross section for worst case design lowers due
> to etching and plating variances.
> 
> This would leave the VccInt limit for the package something in the area
> of 15-25A using std tables and assuming a lot about the carrier pcb -
> or about 18-30W. Probably a LOT less as this isn't free air and one
> side is up against the hot die under worst case load, and the other
> side is insulated with the host PCB FR-4 providing little cooling for
> the IR heating in the traces/vias.

  You'll have old/partly dead FPGAs on PCBs ? - wire one backwards, so 
the substrate diode heats, and do some destructive tests
- thermal and fusing....

> 
> Clearly a dense RC design at modest frequencies can easily exceed this
> in dynamic power.

  OK - So we accept that the extreme case ceiling is going to be 'C 
detemined  ( rather than simple Max_MHz ).
  That means you design the system with the most aggressive thermal, and
current policies you can afford.

  Then, you test it - and have sensors that mean you can run to the 
envelope edges ?

  If you can then prove that the 'C is leaving a lot of MHz behind, in
working, real case, designs - then Xilinx will probably be
quite interested in finding better thermal package solutions.

  Intel spends a LOT of money on thermal and current aspects.

-jg