BGA central ground matrix

Typically FPGA BGAs have a central square of balls which are all connected 
to ground. What is the current wisdom on how to hookup the PCB tracking for 
the central ground matrix.

The simplest, and lowest inductance, seems to be to put down a solid square 
of copper covering the central ground ball pads, and pepper the square with 
ground vias. But that looks like the dreaded 'Solder Mask Defined' pads. Is 
it better to go with individual NSMD pads, tracking, and vias?

Thanks. 

Tim,,

That is so last year.

Howard Johnson showed that the loops need to be made small.

As it turns out all ranks of connections inside the square carry no 
current at all.  Solve Maxwell's equations, and surprise!

So, alternative power and ground is the best.

That is what our SparseChevron(tm) is all about.

Austin

Tim wrote:
> Typically FPGA BGAs have a central square of balls which are all connected 
> to ground. What is the current wisdom on how to hookup the PCB tracking for 
> the central ground matrix.
> 
> The simplest, and lowest inductance, seems to be to put down a solid square 
> of copper covering the central ground ball pads, and pepper the square with 
> ground vias. But that looks like the dreaded 'Solder Mask Defined' pads. Is 
> it better to go with individual NSMD pads, tracking, and vias?
> 
> Thanks. 
> 
> 

Possibly both missing the point.  Usually the central ground
matrix is for thermal conduction to the ground plane.  Check
with your assembly service, but usually placing a solid plane
under the BGA with solder mask defined openings will adversely
affect soldering.  We usually use etch at about the pad size
going diagonally to one via per pad.  No thermal relief where
the via attaches to the ground plane(s).

Central ground balls in these packages do carry DC current,
but were placed where they are for better thermal conduction to
a central die.  Generally many more signal return grounds
appear in the outer sections of the same BGA's.

Also check with the chip manufacturer for possible application
information.  I've also seen BGA packages with a single
heat slug on the bottom requiring a special pad and solder
paste pattern (Broadcom Gig ethernet PHY).  A BGA that
has sufficient thermal conductivity to the top surface usually
works best with a heatsink rather than using the circuit
board for heat spreading (Xilinx flip-chip metal top packs).

Regards,
Gabor

austin wrote:
> Tim,,
>
> That is so last year.
>
> Howard Johnson showed that the loops need to be made small.
>
> As it turns out all ranks of connections inside the square carry no
> current at all.  Solve Maxwell's equations, and surprise!
>
> So, alternative power and ground is the best.
>
> That is what our SparseChevron(tm) is all about.
>
> Austin
>
> Tim wrote:
> > Typically FPGA BGAs have a central square of balls which are all connected
> > to ground. What is the current wisdom on how to hookup the PCB tracking for
> > the central ground matrix.
> >
> > The simplest, and lowest inductance, seems to be to put down a solid square
> > of copper covering the central ground ball pads, and pepper the square with
> > ground vias. But that looks like the dreaded 'Solder Mask Defined' pads. Is
> > it better to go with individual NSMD pads, tracking, and vias?
> > 
> > Thanks. 
> > 
> >

"Gabor" <gabor@alacron.com> wrote

an excellent post! We use a criss-cross pattern of smaller traces going 
between the pads and vias, four narrower traces per gnd pad and per via. 
Makes it look nicer around the edges of the central cluster, but works much 
the same as yours!
Cheers, Syms. 

Austin

This all suggests that I can have an outer ring of vias in the center
of a device (next to every "outer" gnd ball) and a copper pour on the
top layer connecting the rest of the gnd balls with a few vias. I can
then easily put some bulk decoupling right in the center of the bga as
it is no longer peppered with vias. If this is the case then you have
my thanks for pointing this out.

By the way, you say no current flows on the inner balls but surely they
carry their share of the DC current?

Regards

Colin

"colin" <colin_toogood@yahoo.com> wrote in message 
news:1138876017.581870.242570@g43g2000cwa.googlegroups.com...
>
> This all suggests that I can have an outer ring of vias in the center
> of a device (next to every "outer" gnd ball) and a copper pour on the
> top layer connecting the rest of the gnd balls with a few vias. I can
> then easily put some bulk decoupling right in the center of the bga as
> it is no longer peppered with vias. If this is the case then you have
> my thanks for pointing this out.
>
We leave out an occasional via to squeeze in 0805 caps in this centre 
region. Works well on our FG676 parts with, IIRC, a 6x6 centre. The 0805s 
are 2mm long so they fit nicely into the via matrix. The 0805 pads are 
directly aligned with the FPGA GND pads, so the via fit into the gaps.
HTH, Syms.

Colin,

You are making a classic mistake:  not much DC current flows either.

The static magnetic field will force the static electric field to be 
confined to the area adjacent to the current flow in the opposite direction.

This is not skin effect (where current flows on the surface at high 
frequencies), but a very simple EM rule, that is completely ignored!

Use of any 2&1/2 D or 3D (Ansoft) modeling tool shows this.

The most famous (and true) story of this was with the SF Bay Area Rapid 
Transit System (BART), in ~1974 or was it 1975?:

The design had a third rail, on the left of the train (from front of 
train point of view) carrying 1000V DC for the train.

The return was the two rails.

Obviously(?) the Westinghouse engineers reasoned that the return current 
would be equally divided among the two rails.  1/2 on right rail, 1/2 on 
left rail.

They designed a "train in block" detector to show where they had trains 
that detected when the two currents were balanced.

Day 1, they turn it on, and everywhere there is NO train, the light is 
ON (giant status board in Richmond, Ca).  Everywhere there !is! a train, 
the light is OFF!

Westinghouse, Xerox (who did the computers?), and a host of consultants 
descend on UC Berkeley to ask the E&M Professors "what the h***?"

As they (professors) laughed and laughed, they asked the grad and senior 
students to figure it out with (for) the commercial engineers.

So, we all sat down, sharpened our pencils, got out our sliderules and 
textbooks, solved it, and voila!  2/3 in the left rail (nearest to the 
supply) and 1/3 on the right rail (furthest).

Austin

colin wrote:

> Austin
> 
> This all suggests that I can have an outer ring of vias in the center
> of a device (next to every "outer" gnd ball) and a copper pour on the
> top layer connecting the rest of the gnd balls with a few vias. I can
> then easily put some bulk decoupling right in the center of the bga as
> it is no longer peppered with vias. If this is the case then you have
> my thanks for pointing this out.
> 
> By the way, you say no current flows on the inner balls but surely they
> carry their share of the DC current?
> 
> Regards
> 
> Colin
> 

On Thu, 02 Feb 2006 11:48:10 -0800, Austin Lesea <austin@xilinx.com>
wrote:

>The most famous (and true) story of this was with the SF Bay Area Rapid 
>Transit System (BART), in ~1974 or was it 1975?:

I was there in '70 or '71: I remember that the line and stations were
finished, but there was some technical problem that prevented the
trains running.

Austin Lesea wrote:
> .....
> The static magnetic field will force the static electric field to be
> confined to the area adjacent to the current flow in the opposite direction.
>
> .....

Austin,

sure you did not really mean that? Static magnetic fields do not
affect electric field(s) according to physics.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

dp,

Perhaps these folks say it better:

"Proximity Effect"  As true at DC as at any frequency

http://www.cda.org.uk/Megab2/elecapps/pub22/sec4.htm#Proximity%20Effect

Commonly misunderstood.

You tell me what is happening?

I say the DC magnetic field affects current flow.

Austin

dp wrote:

> Austin Lesea wrote:
> 
>>.....
>>The static magnetic field will force the static electric field to be
>>confined to the area adjacent to the current flow in the opposite direction.
>>
>>.....
> 
> 
> Austin,
> 
> sure you did not really mean that? Static magnetic fields do not
> affect electric field(s) according to physics.
> 
> Dimiter
> 
> ------------------------------------------------------
> Dimiter Popoff               Transgalactic Instruments
> 
> http://www.tgi-sci.com
> ------------------------------------------------------
>