Modelsim error when doing: port map(a => not(b))

Hi all,

I'm VERY sorry because I've seen much discussion about globally static
expressions and Modelsim, but I cannot find a clear answer to this
problem.

When you instantiate an entity, is quite common to negate one of the
inputs. It would look something like this:

i_my_entity : MyEntity
port map(
                 ena => not(nEN)
);

When we pass it to Modelsim for pre-synthesis simulation, it complains:
"The actual for formal 'ena' is not a globally static expression".

I don't look for an answer for "why it does not work". I would like to
know HOW can I make it work in a convenient way, different from
assigning not(nEN) to a signal and passing this signal to the
instantiation like this:

signal aNegation : std_logic;
...
aNegation <= not(nEN);
...
i_my_entity : MyEntity
port map(
                 ena => aNegation
);

Regards.
Jose.

Hehehe, I answer to myself (and to those who found the same problem).

I found a possible answer here:

http://groups.google.com/group/comp.lang.vhdl/browse_frm/thread/c7a753ad13b31cc/5a955217c17a88f0?lnk=st&q=port+map+not&rnum=4&hl=en#5a955217c17a88f0

The trick seems to be enclosing the NOT like this:

i_my_entity : MyEntity
port map(
                 ena => "not"(nEN)
);

I'm trying now if it works, but what I can tell you for sure is that
Modelsims compiles it.

Regards.
Jose.