FPGA growth vs. ASIC growth

I have been searching around online for a good comparison of the growth 
rates of FPGAs and ASICs (specifically gate size, power consumption per 
gate, cost per gate, and clock speed).  I am trying to show the gap 
narrowing between these two over time.  I have yet to find any good 
information, and even raw data would be very useful.  Is there any such 
comparison anyone has seen?  If not, does anyone know of a good place to 
find this type of raw data and historical pricing for FPGAs?  I seem to 
be completely unable to find ASIC equivalent gate ratings for most FPGAs.

Thanks in advance.

On Fri, 03 Feb 2006 00:52:20 -0800, Caleb Leak <dornif@gmail.com>
wrote:

> I am trying to show the gap 
>narrowing between these two over time. 

Why would it narrow? At first sight, it should stay constant. For a
given FPGA technology, the differences are simply due to the extra die
resources required to implement a programmable feature as opposed to a
fixed feature. This difference should stay constant as both the FPGA
and ASIC move to new processes. 

The obvious differential is that the larger FPGA companies will be
able to take advantage of a new process earlier than most ASIC
customers. However, as process lifetimes increase (about 5 years now?)
this differential decreases, rather than increasing. Besides, it's not
in the interest of the fabs to only have a handful of customers on a
new process; they want everybody on it.

Another factor to take into account is that the FPGA vendor's
cutting-edge devices - the first ones on 90nm, for example - are
invariably large, expensive, and low yield, and so probably not useful
to most customers. So, it could even be argued that the ability to
take advantage of new processes isn't actually that useful anyway.

As a purely technical or technological subject, this comparison is
meaningless, for every FPGA is actually designed as an ASIC. The
difference between FPGA and ASIC, and the reason why the former is
growing and the latter is lingering, is economics.
Not too many potential ASIC users can afford to invest $50 M or 200
man-years in the development of a state-of-the-art ASIC, but Xilinx and
Altera can, and do. They design a basic FPGA that can easily be
"step-and-repeated" to generate a whole FPGA family that over its life
(of not too many years) results in sales of several Billion dollars.
That business model works very well for Xilinx and Altera.  Ask any
investor in LSI Logic how well the ASIC business is doing...
When Paul writes:
> Another factor to take into account is that the FPGA vendor's
> cutting-edge devices - the first ones on 90nm, for example - are
> invariably large, expensive, and low yield, and so probably not useful
> to most customers. So, it could even be argued that the ability to
> take advantage of new processes isn't actually that useful anyway.

I suggest to look at the Spartan-3 family, our highest-running 90-nm
family. Few designers would call Spartan-3 "large, expensive, and low
yield,,,and not useful for most customers"
Every new process has a learning curve, but that works in favor of
FPGAs, since only they create the enormous volumes that drive yield up
and cost down.

In short, FPGA vs ASIC is not a question of technology, but largely of
economics and risk tolerance.
ASICs are for extreme applications: extreme quantity, extreme
complexity, extreme speed, and extremely low power. In most other
applications, FPGAs (or other standard parts) are an increasingly
popular alternative. I see the FPGA, microprocessor, and ASSP as the
obvious choices by default, ASIC is the exception that must be
justified in each individual case.
But then I admit to being biased...
Peter Alfke, Xilinx

Peter Alfke wrote:

> As a purely technical or technological subject, this comparison is
> meaningless, for every FPGA is actually designed as an ASIC.

Nitpick, but why does the "Application Specific" in "ASIC" apply to an
FPGA and not to a Pentium, when the FPGA nails down the specificity of
application far less than a processor would?

Well, acronyms are sometimes silly. RAM says random access (which every
ROM has), and should really be Read/Write Memory.
ASIC seems to stand for a design that is specifically designed for/by
one customer, while an ASSP is a standard part for a popular function.
Don' read too much into the TLA (three-letter-acronym).
Peter Alfke

Paul Johnson wrote:
> On Fri, 03 Feb 2006 00:52:20 -0800, Caleb Leak <dornif@gmail.com>
> wrote:
>
> > I am trying to show the gap
> >narrowing between these two over time.
>
> Why would it narrow? At first sight, it should stay constant. For a
> given FPGA technology, the differences are simply due to the extra die
> resources required to implement a programmable feature as opposed to a
> fixed feature. This difference should stay constant as both the FPGA
> and ASIC move to new processes.

technically it may not change, but in practice it might for some
applications.
Unless the ASIC volume is huge I may not make sense to spend the huge
NRE to
get in the lastest process (what's the price of a 90nm mask set?
500K$?)
FPGAs are generic so they have the volume to take advantage of the
newest process.

-Lasse

Lasse,

500K$?

What a deal.  Where can you get a 90nm mask set for that price?

We have seen studies that development and productization of a 90nm chip 
costs from 70 to 180 Million $ (US).

I can not comment on how much it costs Xilinx, but if you look at our 
R&D spending as a percentage of revenues from our public stock and 
business reports, those numbers are in the right magnitude range.

Like they say about Opera, it is all over when the fat lady sings.  So 
it is with ASICs "heyday".  The singing is over.  The growth is entirely 
negative.  The ASIC starts are shrinking by a factor of ten per year.

Now ASSPs are still doing very well, as a standard product still is a 
money maker, even with these high development costs.  And a standard 
product costs a lot less when the die is 1/2 the area in the latest 
technology....

Austin

On 3 Feb 2006 09:25:41 -0800, "Peter Alfke" <peter@xilinx.com> wrote:

>Not too many potential ASIC users can afford to invest $50 M or 200
>man-years in the development of a state-of-the-art ASIC

To be fair, almost nobody spends these figures. You can get into the
ASIC game for as little as $100K in NRE plus, say, $50K in tools. All
those graphs I've ever seen showing a cross-over point at 10's of K
pieces are complete nonsense. These are real numbers for a .11um
structured ASIC.

>I suggest to look at the Spartan-3 family, our highest-running 90-nm
>family. Few designers would call Spartan-3 "large, expensive, and low
>yield,,,and not useful for most customers"

Well, no, and nor would I; I like them. If you want to know what I
mean try to get sensible quotes and lead times on an XC4VFX20,
XC4VFX40 or XC4VLX80 (not random choices - three I've tried to get
quotes on recently).

>ASICs are for extreme applications: extreme quantity, extreme
>complexity, extreme speed, and extremely low power.

Not exactly fair. I've spent a lot of time looking (and doing), and my
rule of thumbs are, more or less:

1) FPGAs top out at about 750K 'real' gates, and about 40-80MHz real
system speeds. Anything beyond this is too expensive (unless you've
got *really* small volumes) or too difficult. Yes, I know everybody is
going to argue about the exact figures.

2) 1M - ~4M 'real' gates, 75-250MHz, ~1500 pcs/yr for 3 years =>
structured ASIC, no brainer

3) 4M+ gates, 300MHz+, ~3K pcs/yr for 3 years => standard cell

4) If you're going to spend $500K over 3 years (NRE + device costs)
then the structured ASIC vendors will talk to you

5) If you're going to spend $1M over 3 years (NRE + device costs) then
the standard cell vendors will talk to you

Of course, for options 2- 5 you need to buy real tools, and you need
to know how to verify.

>But then I admit to being biased...

Indeed...  :)

PS - if anybody out there wants to subcontract a structured ASIC
conversion, reply and I'll send you a real email address. Sorry,
Peter...  :)

The big dedicated players, LSI Logic, Xilinx, Altera, Lattice, Actel,
et.al. are all publicly traded companies.
If you want to check on their success, just watch their relative stock
performance.
The beauty of capitalism: hot air does not help, the Bottom Line speaks
clearly.
Peter Alfke

On Fri, 03 Feb 2006 14:04:43 -0800, Austin Lesea <austin@xilinx.com>
wrote:

>Lasse,
>
>500K$?
>
>What a deal.  Where can you get a 90nm mask set for that price?

Have you actually got a quote for a 90nm mask set? Can you find a real
number on the web for a real mask price? I'm willing to bet the answer
to both of those is no. $500K was the standard figure going around the
web 5 years ago, when 90nm was new. And how many masks did that cover?
35? How many masks does the average ASIC developer pay for? 5?

>We have seen studies that development and productization of a 90nm chip 
>costs from 70 to 180 Million $ (US).
>I can not comment on how much it costs Xilinx, but if you look at our 
>R&D spending as a percentage of revenues from our public stock and 
>business reports, those numbers are in the right magnitude range.

According to Gartner Dataquest, 20% of all design starts in the
Americas are now at 90nm. Correct me if I'm wrong, but my guess is
that Xilinx is responsible for about 1% of design starts in the
Americas. The other guys are not paying 70 - $180M.

>Like they say about Opera, it is all over when the fat lady sings.  So 
>it is with ASICs "heyday".  The singing is over.  The growth is entirely 
>negative.  The ASIC starts are shrinking by a factor of ten per year.

Austin, that's just nonsense. No-one has the real numbers, but there
is general agreement - IIRC, it's about a year since I collected the
figures - that starts have dropped from ~10k/year to a figure of
between 2K and 4K/year, *over 5 years*. The analyst who came came up
with the 2K figure also ignored ASSPs, which makes no sense. ASSPs
*are* ASICs. He's also ignored the fact that ASIC starts are clearly
going to decrease because people roll a number of existing devices
into one larger device. The figures were also compiled at a time when
no-one was going into 90nm because of the complexity. See any number
of commentaries by Gartner. Everyone knows that the real revenue is in
ASICs, not FPGAs. Gartner also says that the ASIC market *grew* 11% in
2004. 

>Now ASSPs are still doing very well, as a standard product still is a 
>money maker, even with these high development costs.  And a standard 
>product costs a lot less when the die is 1/2 the area in the latest 
>technology....

FPGAs form a small part of the totality of ASSPs. IIRC, there are
currently about 2000 ASSP design starts a year. And yes, of course,
they all get better in new technologies.

Come on, guys, this is not a Xilinx marketing forum. Perhaps you could
credit us with a little more intelligence.