realize pci in fpga

hi,all.
I am realize pci target core in fpga(cyclone),but there are some
questions.
1,I don't know what type pin should pci_clk be,normal io or clk of
fpga?
2,I series 50ohm resistors between pci connector and fpga,does this
bring some problems? the goal is to make it suitable for 3.3v and 5v.
thanks.

eehinjor wrote:

> hi,all.
> I am realize pci target core in fpga(cyclone),but there are some
> questions.
> 1,I don't know what type pin should pci_clk be,normal io or clk of
> fpga?
> 2,I series 50ohm resistors between pci connector and fpga,does this
> bring some problems? the goal is to make it suitable for 3.3v and 5v.
> thanks.
> 


Cyclone is not compatible with PCI 5v, the voltage transients
exceed 5v and will damage the device.

You will need to use IDT Quickswitch or similar device to
limit the input voltage to your Cyclone in a 5v scenario.

Google for PCI and quickswitch, you should find a Xilinx
app's note on the subject.

Alan

Alan Myler wrote:
> 
> Cyclone is not compatible with PCI 5v, the voltage transients
> exceed 5v and will damage the device.
> 
> You will need to use IDT Quickswitch or similar device to
> limit the input voltage to your Cyclone in a 5v scenario.
> 
> Google for PCI and quickswitch, you should find a Xilinx
> app's note on the subject.
> 

... or look a the schematics for the Altera Cyclone PCI development kits.

	-hpa

H. Peter Anvin wrote:
> ... or look a the schematics for the Altera Cyclone PCI development kits.
>
> 	-hpa

Finding is better than looking....

ftp://ftp.altera.com/outgoing/devkit/PCI_DK_2C35/schem_cii_pcidevbd_b.pdf

Karl.

Thanks all.
>From the datasheet of cyclone,it is compatible with pci-5v by diode and
risistors.

Can somebody help me to solve the first question?

it should trace through to the clock pin this allows better us in the FPGA 
fabric, we have applied this to our development boards so that the PCI clock 
can be used as the system clock if the user so wishes

REGARDS IAN

Enterpoint Ltd:      Home of the Low-Cost development board RAGGEDSTONE1
Website:               www.enterpoint.co.uk

"eehinjor" <eehinjor@163.com> wrote in message 
news:1139408642.434006.277270@g43g2000cwa.googlegroups.com...
> Thanks all.
>>From the datasheet of cyclone,it is compatible with pci-5v by diode and
> risistors.
>
> Can somebody help me to solve the first question?
> 

Thank you.Ian Muncaster.
By the way,
In the spec:the length of CLK is 2.5inches +-0.1inch.
if there is a qs3861 or resistor between connector and fpga,how can I
calculator the length of PCB-trace?

RIGHT this is some calculation:

Wouldn't advise using a resistor?

For the QS381 the maximum propagation is 250ps, using a signal propagation 
of 1ns equals 12inches for lightly loaded line or 3inches for a loaded line 
(using bus switch most likely means lightly loaded) we can work out the 
equivalent trace length the bus switch would represent.

Doing this you would find that this fails the PCI spec, we have seen no 
problems if you just make sure your clock trace is longer than your worst 
case for the rest of the bus.  This means that the setup and hold times are 
met.



"eehinjor" <eehinjor@163.com> wrote in message 
news:1139485190.614959.181580@o13g2000cwo.googlegroups.com...
> Thank you.Ian Muncaster.
> By the way,
> In the spec:the length of CLK is 2.5inches +-0.1inch.
> if there is a qs3861 or resistor between connector and fpga,how can I
> calculator the length of PCB-trace?
> 

Thank you for your response so soon.
250ps is about 3inches,but the length of clk can not be longer than
2.5+0.1inches.
how can that meet the spec?

It doesnt meat the spec thats what im saying, this area is one of the major 
problems with PCI and 3.3v systems such as your FPGA, as i said in our 
development boards we make sure the rest of the PCI bus meets there 
specification and then make sure the trace lengths of the clock signal 
either side of the bus switch is longer than your worst case by 0.5inches or 
greater.
This works for our systems and we have seen no problems,  making the trace 
longer ensures you meet the set up and hold times for the rest of the bus.

This is no given thing it what we have seen working.

REGARDS IAN

"eehinjor" <eehinjor@163.com> wrote in message 
news:1139487456.386069.198790@g47g2000cwa.googlegroups.com...
> Thank you for your response so soon.
> 250ps is about 3inches,but the length of clk can not be longer than
> 2.5+0.1inches.
> how can that meet the spec?
>