Hello I recently designed a basic serial in parallel out IO board that used an Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as expected and everything was fine. I found that I could purchase the 7128slc84-15 chip for about half the price so I did, and now my same setup doesnt work. I recompiled the VHDL for the 15 speed grade chip without any problems and yet it does not run my program correctly. I have loaded a small test program on the 15 chip and it works fine and does what it should. My code is using an external clock to run the state machine so I dont understand why it makes any difference whether I use a -10 or a -15.. What should I look for to make this 15 grade chip run my code without problems?? Does a jump in speed make that big of a difference?
why does speed grade effect VHDL program??
Started by ●February 7, 2006
Reply by ●February 7, 20062006-02-07
"Matt Clement" <clement@nanotechsys.com> wrote in message news:%V3Gf.8650$Gg1.8100@trnddc03...> Hello > > I recently designed a basic serial in parallel out IO board that used an > Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as > expected and everything was fine. I found that I could purchase the > 7128slc84-15 chip for about half the price so I did, and now my same setup > doesnt work. I recompiled the VHDL for the 15 speed grade chip without > any problems and yet it does not run my program correctly. I have loaded > a small test program on the 15 chip and it works fine and does what it > should. My code is using an external clock to run the state machine so I > dont understand why it makes any difference whether I use a -10 or > a -15.. > > What should I look for to make this 15 grade chip run my code without > problems?? Does a jump in speed make that big of a difference?Three questions: Did you respecify the -15 speed grade in the Quartus-II tool and do a complete recompile? How fast does the Quartus-II tool tell you your design can run? How fast is the clock you're providing?
Reply by ●February 7, 20062006-02-07
Hello John and thanks for the quick reply. 1. Yes I redefined the device to the -15 chip and recompiled the design in quartus-II. 2. after compiling the -15 it says internal clk fmax is 41.67Mhz and with it set as a -10 it says fmax is 51.02Mhz. 3. the external clock driving the state machine in the chip is only 5MHZ. "John_H" <johnhandwork@mail.com> wrote in message news:%84Gf.23953$wk5.16427@news02.roc.ny...> "Matt Clement" <clement@nanotechsys.com> wrote in message > news:%V3Gf.8650$Gg1.8100@trnddc03... >> Hello >> >> I recently designed a basic serial in parallel out IO board that used an >> Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as >> expected and everything was fine. I found that I could purchase the >> 7128slc84-15 chip for about half the price so I did, and now my same >> setup doesnt work. I recompiled the VHDL for the 15 speed grade chip >> without any problems and yet it does not run my program correctly. I >> have loaded a small test program on the 15 chip and it works fine and >> does what it should. My code is using an external clock to run the state >> machine so I dont understand why it makes any difference whether I use >> a -10 or a -15.. >> >> What should I look for to make this 15 grade chip run my code without >> problems?? Does a jump in speed make that big of a difference? > > Three questions: > Did you respecify the -15 speed grade in the Quartus-II tool and do a > complete recompile? > How fast does the Quartus-II tool tell you your design can run? > How fast is the clock you're providing? >
Reply by ●February 7, 20062006-02-07
Matt Clement wrote: (top posting fixed)> "John_H" <johnhandwork@mail.com> wrote in message > news:%84Gf.23953$wk5.16427@news02.roc.ny... > >>"Matt Clement" <clement@nanotechsys.com> wrote in message >>news:%V3Gf.8650$Gg1.8100@trnddc03... >> >>>Hello >>> >>>I recently designed a basic serial in parallel out IO board that used an >>>Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as >>>expected and everything was fine. I found that I could purchase the >>>7128slc84-15 chip for about half the price so I did, and now my same >>>setup doesnt work. I recompiled the VHDL for the 15 speed grade chip >>>without any problems and yet it does not run my program correctly. I >>>have loaded a small test program on the 15 chip and it works fine and >>>does what it should. My code is using an external clock to run the state >>>machine so I dont understand why it makes any difference whether I use >>>a -10 or a -15.. >>> >>>What should I look for to make this 15 grade chip run my code without >>>problems?? Does a jump in speed make that big of a difference? >> >>Three questions: >> Did you respecify the -15 speed grade in the Quartus-II tool and do a >>complete recompile? >> How fast does the Quartus-II tool tell you your design can run? >> How fast is the clock you're providing? >> >> Hello John and thanks for the quick reply. > > 1. Yes I redefined the device to the -15 chip and recompiled the > design in quartus-II. > 2. after compiling the -15 it says internal clk fmax is 41.67Mhz > and with it set as a -10 it says fmax is 51.02Mhz. > 3. the external clock driving the state machine in the chip is only > 5MHZ. > As I read your post alarm bells started ringing, and I haven't been able to turn them off. The trigger was the phrase "run my program". It sounds like you are a software engineer without much experience with FPGA designs? You cannot think of that body of HDL code you've written as a 'program'. It's not. The 'D' in HDL stands for the 'description' of the logic that you want -- _not_ a 'program'. If you are clocking this thing at 5MHz and it fails to work, even though it thinks it can work at 42MHz, there is something that the tool is overlooking that you must help it with. You are probably violating a timing parameter that is not adequately described to your tool, and which you'll have to look at yourself. So here's some questions: What form of serial are you giving the thing? Is it synchronous? Could you be violating setup or hold requirements going from serial to parallel? Is your 5MHz clock your only clock (no 'strobe' inputs?) Did I leave something out? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●February 7, 20062006-02-07
Matt Have you got any inputs that are not synchronous to your state machine, or you are not meeting setup and hold requirements? As well as clocking slower the set, hold and clock to output times will vary with speed grade as silicon batch variations. John Adair Enterpoint Ltd. - Soon to be the home of Hollybush1. The PC104Plus Spartan-3 Development Platform. http://www.enterpoint.co.uk "Matt Clement" <clement@nanotechsys.com> wrote in message news:Ox4Gf.137364$7l4.100383@trnddc05...> Hello John and thanks for the quick reply. > > 1. Yes I redefined the device to the -15 chip and recompiled the design > in quartus-II. > 2. after compiling the -15 it says internal clk fmax is 41.67Mhz and > with it set as a -10 it says fmax is 51.02Mhz. > 3. the external clock driving the state machine in the chip is only 5MHZ. > > > "John_H" <johnhandwork@mail.com> wrote in message > news:%84Gf.23953$wk5.16427@news02.roc.ny... >> "Matt Clement" <clement@nanotechsys.com> wrote in message >> news:%V3Gf.8650$Gg1.8100@trnddc03... >>> Hello >>> >>> I recently designed a basic serial in parallel out IO board that used an >>> Altera MAX 7128slc84-10 chip. I was able to reliably get it to run as >>> expected and everything was fine. I found that I could purchase the >>> 7128slc84-15 chip for about half the price so I did, and now my same >>> setup doesnt work. I recompiled the VHDL for the 15 speed grade chip >>> without any problems and yet it does not run my program correctly. I >>> have loaded a small test program on the 15 chip and it works fine and >>> does what it should. My code is using an external clock to run the state >>> machine so I dont understand why it makes any difference whether I use >>> a -10 or a -15.. >>> >>> What should I look for to make this 15 grade chip run my code without >>> problems?? Does a jump in speed make that big of a difference? >> >> Three questions: >> Did you respecify the -15 speed grade in the Quartus-II tool and do a >> complete recompile? >> How fast does the Quartus-II tool tell you your design can run? >> How fast is the clock you're providing? >> > >
Reply by ●February 7, 20062006-02-07
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:746dnfeoHM1sRHXenZ2dnUVZ_tidnZ2d@web-ster.com...> Is your 5MHz clock your only clock (no 'strobe' inputs?) >To add to Tim's comments, have you gated this clock? Cheers, Syms.
Reply by ●February 7, 20062006-02-07
Symon wrote:> "Tim Wescott" <tim@seemywebsite.com> wrote in message > news:746dnfeoHM1sRHXenZ2dnUVZ_tidnZ2d@web-ster.com... > >>Is your 5MHz clock your only clock (no 'strobe' inputs?) >> > > To add to Tim's comments, have you gated this clock? > Cheers, Syms. > >Symon: Are you assuming a faster clock that could be used to gate the 5MHz one? Somehow I think that's Matt's _only_ clock. Matt: Have you met the rise and fall time specifications for the clock? I would expect this would cause more problems with a higher speed grade, but since the chips are binned it could just be that the lower speed grade parts have more skew which may or may not make them more sensitive to rise and fall times. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●February 7, 20062006-02-07
Hello everyone and many thanks for the replies.
I am a fairly "generic" guy so excuse my "generic" reference to the program.
I am an EE with specialization in digital logic design. The serial is a
basic bit bang serial 32 bit stream that relates to 32 inputs. I simply
read them in serially and then dump them parallel to 32 LED's. The clock
for the serial data is provided by the source system and its 5 Mhz. The
simulation of the "program" in Quartus verifies that it should be doing
exactly what I want (in theory..haha). It works fine with the -10 part but
when I swap with a compiled, programmed -15 it fails to function. I would
have thought the -15 would be faster but according to the compiler, it's
Fmax is slower. The simulation for the -15 also works fine. I spent the
better part of the morning scratching my head over this one.
here is the basic "program"
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLONE34 IS
PORT
(clk : IN BIT;
SEL : IN BIT_VECTOR(7 DOWNTO 0);
ADD : IN BIT_VECTOR(5 DOWNTO 0);
DAT : INOUT BIT_VECTOR(1 DOWNTO 0);
LED1 : OUT BIT_VECTOR(31 DOWNTO 0));
END CLONE34;
ARCHITECTURE ONE OF CLONE34 IS
TYPE STATE_TYPE IS
(IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34);
SIGNAL STATE: STATE_TYPE;
BEGIN
PROCESS (clk, ADD)
VARIABLE DATA : BIT_VECTOR(35 DOWNTO 0);
BEGIN
IF (clk'EVENT AND clk = '1')THEN
DAT(0)<='0';
CASE STATE IS
WHEN IDLE =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(35):=SEL(1);
STATE<=S0;
ELSE
STATE<=IDLE;
END IF;
WHEN S0 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(34):=SEL(1);
STATE <= S1;
ELSE
STATE<=IDLE;
END IF;
WHEN S1 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(33):=SEL(1);
STATE <= S2;
ELSE
STATE<=IDLE;
END IF;
WHEN S2 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(32):=SEL(1);
STATE <= S3;
ELSE
STATE<=IDLE;
END IF;
WHEN S3 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(31):=SEL(1);
STATE <= S4;
ELSE
STATE<=IDLE;
END IF;
WHEN S4 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(30):=SEL(1);
STATE <= S5;
ELSE
STATE<=IDLE;
END IF;
WHEN S5 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(29):=SEL(1);
STATE <= S6;
ELSE
STATE<=IDLE;
END IF;
WHEN S6 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(28):=SEL(1);
STATE <= S7;
ELSE
STATE<=IDLE;
END IF;
WHEN S7 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(27):=SEL(1);
STATE <= S8;
ELSE
STATE<=IDLE;
END IF;
WHEN S8 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(26):=SEL(1);
STATE <= S9;
ELSE
STATE<=IDLE;
END IF;
WHEN S9 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(25):=SEL(1);
STATE <= S10;
ELSE
STATE<=IDLE;
END IF;
WHEN S10 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(24):=SEL(1);
STATE <= S11;
ELSE
STATE<=IDLE;
END IF;
WHEN S11 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(23):=SEL(1);
STATE <= S12;
ELSE
STATE<=IDLE;
END IF;
WHEN S12 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(22):=SEL(1);
STATE <= S13;
ELSE
STATE<=IDLE;
END IF;
WHEN S13 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(21):=SEL(1);
STATE <= S14;
ELSE
STATE<=IDLE;
END IF;
WHEN S14 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(20):=SEL(1);
STATE <= S15;
ELSE
STATE<=IDLE;
END IF;
WHEN S15 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(19):=SEL(1);
STATE <= S16;
ELSE
STATE<=IDLE;
END IF;
WHEN S16 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(18):=SEL(1);
STATE <= S17;
ELSE
STATE<=IDLE;
END IF;
WHEN S17 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(17):=SEL(1);
STATE <= S18;
ELSE
STATE<=IDLE;
END IF;
WHEN S18 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(16):=SEL(1);
STATE <= S19;
ELSE
STATE<=IDLE;
END IF;
WHEN S19 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(15):=SEL(1);
STATE <= S20;
ELSE
STATE<=IDLE;
END IF;
WHEN S20 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(14):=SEL(1);
STATE <= S21;
ELSE
STATE<=IDLE;
END IF;
WHEN S21 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(13):=SEL(1);
STATE <= S22;
ELSE
STATE<=IDLE;
END IF;
WHEN S22 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(12):=SEL(1);
STATE <= S23;
ELSE
STATE<=IDLE;
END IF;
WHEN S23 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(11):=SEL(1);
STATE <= S24;
ELSE
STATE<=IDLE;
END IF;
WHEN S24 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(10):=SEL(1);
STATE <= S25;
ELSE
STATE<=IDLE;
END IF;
WHEN S25 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(9):=SEL(1);
STATE <= S26;
ELSE
STATE<=IDLE;
END IF;
WHEN S26 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(8):=SEL(1);
STATE <= S27;
ELSE
STATE<=IDLE;
END IF;
WHEN S27 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(7):=SEL(1);
STATE <= S28;
ELSE
STATE<=IDLE;
END IF;
WHEN S28 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(6):=SEL(1);
STATE <= S29;
ELSE
STATE<=IDLE;
END IF;
WHEN S29 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(5):=SEL(1);
STATE <= S30;
ELSE
STATE<=IDLE;
END IF;
WHEN S30 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(4):=SEL(1);
STATE <= S31;
ELSE
STATE<=IDLE;
END IF;
WHEN S31 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(3):=SEL(1);
STATE <= S32;
ELSE
STATE<=IDLE;
END IF;
WHEN S32 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(2):=SEL(1);
STATE <= S33;
ELSE
STATE<=IDLE;
END IF;
WHEN S33 =>
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(1):=SEL(1);
STATE <= S34;
ELSE
STATE<=IDLE;
END IF;
WHEN S34 =>
DAT(0)<='1';
IF ADD = SEL(7 DOWNTO 2) THEN
DATA(0):=SEL(1);
STATE <= IDLE;
--THIS IS WHERE WE WOULD DO OUR PARITY CHECK FOR INCOMING DATA
--DATA(35,34,33,32) = PARITY4,3,2,1
--IF PARITY1=BLAH BLAH AND
-- PARITY2=BLAH BLAH AND
-- PARITY3=BLAH BLAH AND
-- PARITY4=BLAH BLAH THEN
LED1(31 downto 0)<=DATA(31 downto 0);
--END IF;
ELSE
STATE<=IDLE;
END IF;
END CASE;
ELSE
END IF;
END PROCESS;
END ONE;
"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in
message news:1139333636.27736.0@lotis.uk.clara.net...
> Matt
>
> Have you got any inputs that are not synchronous to your state machine, or
> you are not meeting setup and hold requirements? As well as clocking
> slower the set, hold and clock to output times will vary with speed grade
> as silicon batch variations.
>
> John Adair
> Enterpoint Ltd. - Soon to be the home of Hollybush1. The PC104Plus
> Spartan-3 Development Platform.
> http://www.enterpoint.co.uk
>
>
> "Matt Clement" <clement@nanotechsys.com> wrote in message
> news:Ox4Gf.137364$7l4.100383@trnddc05...
>> Hello John and thanks for the quick reply.
>>
>> 1. Yes I redefined the device to the -15 chip and recompiled the design
>> in quartus-II.
>> 2. after compiling the -15 it says internal clk fmax is 41.67Mhz and
>> with it set as a -10 it says fmax is 51.02Mhz.
>> 3. the external clock driving the state machine in the chip is only
>> 5MHZ.
>>
>>
>> "John_H" <johnhandwork@mail.com> wrote in message
>> news:%84Gf.23953$wk5.16427@news02.roc.ny...
>>> "Matt Clement" <clement@nanotechsys.com> wrote in message
>>> news:%V3Gf.8650$Gg1.8100@trnddc03...
>>>> Hello
>>>>
>>>> I recently designed a basic serial in parallel out IO board that used
>>>> an Altera MAX 7128slc84-10 chip. I was able to reliably get it to run
>>>> as expected and everything was fine. I found that I could purchase the
>>>> 7128slc84-15 chip for about half the price so I did, and now my same
>>>> setup doesnt work. I recompiled the VHDL for the 15 speed grade chip
>>>> without any problems and yet it does not run my program correctly. I
>>>> have loaded a small test program on the 15 chip and it works fine and
>>>> does what it should. My code is using an external clock to run the
>>>> state machine so I dont understand why it makes any difference whether
>>>> I use a -10 or a -15..
>>>>
>>>> What should I look for to make this 15 grade chip run my code without
>>>> problems?? Does a jump in speed make that big of a difference?
>>>
>>> Three questions:
>>> Did you respecify the -15 speed grade in the Quartus-II tool and do a
>>> complete recompile?
>>> How fast does the Quartus-II tool tell you your design can run?
>>> How fast is the clock you're providing?
>>>
>>
>>
>
>
Reply by ●February 7, 20062006-02-07
Okay guys According to the datasheet the -15 is slower than the -10. The prop delay max for each is 10ns and 15ns thus the speed grades. So the slower speed by 5ns is causing it to fail on the slower chip.....hmmm. The setup and hold times for the system are around 100ns so I dont know why its causing so much trouble. Matt "Matt Clement" <clement@nanotechsys.com> wrote in message news:vw5Gf.9710$In4.2864@trnddc06...> Hello everyone and many thanks for the replies. > > I am a fairly "generic" guy so excuse my "generic" reference to the > program. I am an EE with specialization in digital logic design. The > serial is a basic bit bang serial 32 bit stream that relates to 32 > inputs. I simply read them in serially and then dump them parallel to 32 > LED's. The clock for the serial data is provided by the source system and > its 5 Mhz. The simulation of the "program" in Quartus verifies that it > should be doing exactly what I want (in theory..haha). It works fine with > the -10 part but when I swap with a compiled, programmed -15 it fails to > function. I would have thought the -15 would be faster but according to > the compiler, it's Fmax is slower. The simulation for the -15 also works > fine. I spent the better part of the morning scratching my head over > this one. > > here is the basic "program" > > LIBRARY IEEE; > USE IEEE.STD_LOGIC_1164.ALL; > > > ENTITY CLONE34 IS > PORT > (clk : IN BIT; > SEL : IN BIT_VECTOR(7 DOWNTO 0); > ADD : IN BIT_VECTOR(5 DOWNTO 0); > DAT : INOUT BIT_VECTOR(1 DOWNTO 0); > LED1 : OUT BIT_VECTOR(31 DOWNTO 0)); > > END CLONE34; > > ARCHITECTURE ONE OF CLONE34 IS > TYPE STATE_TYPE IS > (IDLE,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,S18,S19,S20,S21,S22,S23,S24,S25,S26,S27,S28,S29,S30,S31,S32,S33,S34); > SIGNAL STATE: STATE_TYPE; > > BEGIN > > PROCESS (clk, ADD) > VARIABLE DATA : BIT_VECTOR(35 DOWNTO 0); > BEGIN > > IF (clk'EVENT AND clk = '1')THEN > > DAT(0)<='0'; > CASE STATE IS > WHEN IDLE => > > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(35):=SEL(1); > STATE<=S0; > > > ELSE > STATE<=IDLE; > > END IF; > > WHEN S0 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(34):=SEL(1); > STATE <= S1; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S1 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(33):=SEL(1); > > STATE <= S2; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S2 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(32):=SEL(1); > > STATE <= S3; > ELSE > STATE<=IDLE; > END IF; > WHEN S3 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(31):=SEL(1); > > STATE <= S4; > ELSE > STATE<=IDLE; > END IF; > WHEN S4 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(30):=SEL(1); > > STATE <= S5; > ELSE > STATE<=IDLE; > END IF; > WHEN S5 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(29):=SEL(1); > > STATE <= S6; > ELSE > STATE<=IDLE; > END IF; > > WHEN S6 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(28):=SEL(1); > > STATE <= S7; > ELSE > STATE<=IDLE; > END IF; > > WHEN S7 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(27):=SEL(1); > > STATE <= S8; > ELSE > STATE<=IDLE; > END IF; > WHEN S8 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(26):=SEL(1); > > STATE <= S9; > ELSE > STATE<=IDLE; > END IF; > > WHEN S9 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(25):=SEL(1); > > STATE <= S10; > ELSE > STATE<=IDLE; > END IF; > WHEN S10 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(24):=SEL(1); > > STATE <= S11; > ELSE > STATE<=IDLE; > END IF; > WHEN S11 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(23):=SEL(1); > > STATE <= S12; > ELSE > STATE<=IDLE; > END IF; > WHEN S12 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(22):=SEL(1); > > STATE <= S13; > ELSE > STATE<=IDLE; > END IF; > WHEN S13 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(21):=SEL(1); > > STATE <= S14; > ELSE > STATE<=IDLE; > END IF; > WHEN S14 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(20):=SEL(1); > > STATE <= S15; > ELSE > STATE<=IDLE; > END IF; > WHEN S15 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(19):=SEL(1); > > STATE <= S16; > ELSE > STATE<=IDLE; > END IF; > WHEN S16 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(18):=SEL(1); > > STATE <= S17; > ELSE > STATE<=IDLE; > END IF; > WHEN S17 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(17):=SEL(1); > > STATE <= S18; > ELSE > STATE<=IDLE; > END IF; > > WHEN S18 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(16):=SEL(1); > > STATE <= S19; > ELSE > STATE<=IDLE; > END IF; > WHEN S19 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(15):=SEL(1); > > STATE <= S20; > ELSE > STATE<=IDLE; > END IF; > > WHEN S20 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(14):=SEL(1); > > STATE <= S21; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S21 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(13):=SEL(1); > > STATE <= S22; > ELSE > STATE<=IDLE; > END IF; > > > > WHEN S22 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(12):=SEL(1); > > STATE <= S23; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S23 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(11):=SEL(1); > > STATE <= S24; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S24 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(10):=SEL(1); > > STATE <= S25; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S25 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(9):=SEL(1); > > STATE <= S26; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S26 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(8):=SEL(1); > > STATE <= S27; > ELSE > STATE<=IDLE; > END IF; > > > > WHEN S27 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(7):=SEL(1); > > STATE <= S28; > ELSE > STATE<=IDLE; > END IF; > > > > WHEN S28 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(6):=SEL(1); > > STATE <= S29; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S29 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(5):=SEL(1); > > STATE <= S30; > ELSE > STATE<=IDLE; > END IF; > > > > WHEN S30 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(4):=SEL(1); > > STATE <= S31; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S31 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(3):=SEL(1); > > STATE <= S32; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S32 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(2):=SEL(1); > > STATE <= S33; > ELSE > STATE<=IDLE; > END IF; > > > WHEN S33 => > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(1):=SEL(1); > > STATE <= S34; > > ELSE > STATE<=IDLE; > END IF; > > WHEN S34 => > DAT(0)<='1'; > IF ADD = SEL(7 DOWNTO 2) THEN > DATA(0):=SEL(1); > > STATE <= IDLE; > > --THIS IS WHERE WE WOULD DO OUR PARITY CHECK FOR INCOMING DATA > --DATA(35,34,33,32) = PARITY4,3,2,1 > --IF PARITY1=BLAH BLAH AND > -- PARITY2=BLAH BLAH AND > -- PARITY3=BLAH BLAH AND > -- PARITY4=BLAH BLAH THEN > > LED1(31 downto 0)<=DATA(31 downto 0); > > --END IF; > > > ELSE > STATE<=IDLE; > > > END IF; > END CASE; > ELSE > > > END IF; > END PROCESS; > END ONE; > > > > > > > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote > in message news:1139333636.27736.0@lotis.uk.clara.net... >> Matt >> >> Have you got any inputs that are not synchronous to your state machine, >> or you are not meeting setup and hold requirements? As well as clocking >> slower the set, hold and clock to output times will vary with speed grade >> as silicon batch variations. >> >> John Adair >> Enterpoint Ltd. - Soon to be the home of Hollybush1. The PC104Plus >> Spartan-3 Development Platform. >> http://www.enterpoint.co.uk >> >> >> "Matt Clement" <clement@nanotechsys.com> wrote in message >> news:Ox4Gf.137364$7l4.100383@trnddc05... >>> Hello John and thanks for the quick reply. >>> >>> 1. Yes I redefined the device to the -15 chip and recompiled the design >>> in quartus-II. >>> 2. after compiling the -15 it says internal clk fmax is 41.67Mhz and >>> with it set as a -10 it says fmax is 51.02Mhz. >>> 3. the external clock driving the state machine in the chip is only >>> 5MHZ. >>> >>> >>> "John_H" <johnhandwork@mail.com> wrote in message >>> news:%84Gf.23953$wk5.16427@news02.roc.ny... >>>> "Matt Clement" <clement@nanotechsys.com> wrote in message >>>> news:%V3Gf.8650$Gg1.8100@trnddc03... >>>>> Hello >>>>> >>>>> I recently designed a basic serial in parallel out IO board that used >>>>> an Altera MAX 7128slc84-10 chip. I was able to reliably get it to run >>>>> as expected and everything was fine. I found that I could purchase >>>>> the 7128slc84-15 chip for about half the price so I did, and now my >>>>> same setup doesnt work. I recompiled the VHDL for the 15 speed grade >>>>> chip without any problems and yet it does not run my program >>>>> correctly. I have loaded a small test program on the 15 chip and it >>>>> works fine and does what it should. My code is using an external clock >>>>> to run the state machine so I dont understand why it makes any >>>>> difference whether I use a -10 or a -15.. >>>>> >>>>> What should I look for to make this 15 grade chip run my code without >>>>> problems?? Does a jump in speed make that big of a difference? >>>> >>>> Three questions: >>>> Did you respecify the -15 speed grade in the Quartus-II tool and do a >>>> complete recompile? >>>> How fast does the Quartus-II tool tell you your design can run? >>>> How fast is the clock you're providing? >>>> >>> >>> >> >> > >
Reply by ●February 7, 20062006-02-07
"Tim Wescott" <tim@seemywebsite.com> wrote in message news:Ur6dnY0U0o5Hf3XenZ2dnUVZ_sWdnZ2d@web-ster.com...> Symon wrote: > >> "Tim Wescott" <tim@seemywebsite.com> wrote in message >> news:746dnfeoHM1sRHXenZ2dnUVZ_tidnZ2d@web-ster.com... >> >>>Is your 5MHz clock your only clock (no 'strobe' inputs?) >>> >> >> To add to Tim's comments, have you gated this clock? >> Cheers, Syms. > Symon: > > Are you assuming a faster clock that could be used to gate the 5MHz one? > Somehow I think that's Matt's _only_ clock. >Hi Tim, I've seen people drive a state machine with a clock, then use the output of this state machine to gate the clock for other bits of circuitry. To make it slower or to save power. Right. Yuk. Sounds like Matt's not doing that, good for him! Cheers, Syms.
