Hi all, As there are number of point tools available in the industry for FPGA based design and implementation, it is becoming more difficult to stick to one flow. Does anybody have some sort of tools tree (2-3 tools against each node in the design flow diagram) available in the industry? This should be independent of any tool vendor but include widely used tools. I mean, I want something like this 1. Design entry Tool1: Tool2: 2. Synthesis Tool1: Leo Spec Tool2: Synplify Pro Tool3:... 3. Code Coverage / Automatic test bench gen. Tool1: ... Tool2: ... 4. Physical synthesis Tool1: ... 5. Place and Route Tool1: ... Tool2:... 6. STA etc..... Thanx in advance, Nagaraj
Tools Tree
Started by ●November 4, 2003
Reply by ●November 4, 20032003-11-04
1. Design entry Tool1: emacs vhdl-mode, verilog mode Tool2: Quartus block diagram 2. Simulation Tool1: Modelsim Tool2: Aldec 3. Synthesis Tool1: Leo Spec Tool2: Synplify Pro Tool3: Quartus Tool4: XST 4. Place and Route Tool1: Xilinx Place & Route + static timing Tool2: Quartus Place & Route + static timing -- Mike Treseler
Reply by ●November 5, 20032003-11-05
I meant much more. For a detailed design flow, including code coverage, DFT, physical synthesis, etc. regards, nagaraj Mike Treseler <tres@tc.fluke.com> wrote in message news:<3FA83665.9030100@tc.fluke.com>...> 1. Design entry > Tool1: emacs vhdl-mode, verilog mode > Tool2: Quartus block diagram > 2. Simulation > Tool1: Modelsim > Tool2: Aldec > 3. Synthesis > Tool1: Leo Spec > Tool2: Synplify Pro > Tool3: Quartus > Tool4: XST > 4. Place and Route > Tool1: Xilinx Place & Route + static timing > Tool2: Quartus Place & Route + static timing > > -- Mike Treseler
Reply by ●November 5, 20032003-11-05
code coverage : tool1: v-navigator from transeda DFT : DftAdvisor for ASIC but for fpga ????. fpga has built-in jtag boundary-scan. So you can download bsdl file for your device. altera: http://www.altera.com/support/devices/bsdl/bsdl.html xilinx: http://www.xilinx.com/support/sw_bsdl.htm other : http://www.acculogic.com/ResourceCenter/Index.htm STA: tool3 : PrimeTime from synopsys physical synthesis: what do you mean ? regards, fe "Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message news:91710219.0311050420.679a7a14@posting.google.com...> I meant much more. For a detailed design flow, including code > coverage, DFT, physical synthesis, etc. > > regards, > nagaraj > > Mike Treseler <tres@tc.fluke.com> wrote in messagenews:<3FA83665.9030100@tc.fluke.com>...> > 1. Design entry > > Tool1: emacs vhdl-mode, verilog mode > > Tool2: Quartus block diagram > > 2. Simulation > > Tool1: Modelsim > > Tool2: Aldec > > 3. Synthesis > > Tool1: Leo Spec > > Tool2: Synplify Pro > > Tool3: Quartus > > Tool4: XST > > 4. Place and Route > > Tool1: Xilinx Place & Route + static timing > > Tool2: Quartus Place & Route + static timing > > > > -- Mike Treseler
Reply by ●November 6, 20032003-11-06
> physical synthesis: > what do you mean ?In the FPGA world this means applying the same synthesis techniques like register re-timing, re-structuring and re-synthesis on a place and routed design. Have a look at Mentor's Precision Physical. I suspect that RTL, Place&Route and Physical will slowly merge into 1 synthesis engine. Given the "close to useless" estimates from wireload models this can't be to soon enough :-) Hans. www.ht-lab.com> regards, > fe > > "Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message > news:91710219.0311050420.679a7a14@posting.google.com... > > I meant much more. For a detailed design flow, including code > > coverage, DFT, physical synthesis, etc. > > > > regards, > > nagaraj > > > > Mike Treseler <tres@tc.fluke.com> wrote in message > news:<3FA83665.9030100@tc.fluke.com>... > > > 1. Design entry > > > Tool1: emacs vhdl-mode, verilog mode > > > Tool2: Quartus block diagram > > > 2. Simulation > > > Tool1: Modelsim > > > Tool2: Aldec > > > 3. Synthesis > > > Tool1: Leo Spec > > > Tool2: Synplify Pro > > > Tool3: Quartus > > > Tool4: XST > > > 4. Place and Route > > > Tool1: Xilinx Place & Route + static timing > > > Tool2: Quartus Place & Route + static timing > > > > > > -- Mike Treseler > >
Reply by ●November 6, 20032003-11-06
In article <3Tvqb.286$QC3.2240@newsfep4-glfd.server.ntli.net>, Hans <hansydelm@no-spam-ntlworld.com> wrote:>In the FPGA world this means applying the same synthesis techniques like >register re-timing, re-structuring and re-synthesis on a place and routed >design. Have a look at Mentor's Precision Physical. I suspect that RTL, >Place&Route and Physical will slowly merge into 1 synthesis engine. Given >the "close to useless" estimates from wireload models this can't be to soon >enough :-) >Hans.The problem with retiming in the FPGA world is not the delay model: You can do it after placement and have a really nice delay model, but the initial conditions model. If you say "keep initial conditions/Global set-reset", its a pain in the butt and needs to be before placement. If you say "Screw initial conditions/global set-reset" it becomes easy and nicely effective, and the designer just has to have his state machine take a startup/reset signal. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
Reply by ●November 10, 20032003-11-10
Synthesis : 1.XST 2.Mentor Leo Spec 3.mentor Precision RTL 4. Synplicity Synplify /Pro 5. Synopsys FPGA Compiler II 6. Synopsys Design Compiler Physical Optimization /Synthesis: 1. Mentor Precision Physical 2. Synplicity Amplify 3. Magma (acquired from Aplus) Design PALACE 4. HDI PlanAhead Simulation (HDL) 1. ModelSim 2. Cadence Verilog XL, NC-Sim 3. Synopsys VCS Formal Verification: 1. Synopsys Formality 2. Verplex (now Cadence) Conformal-FPGA Co-design: 1. Mentor Seamless Schematic: 1. Mentor Design architect 2. Innoveda 3. Cadence concept Board level timing 1. Mentor Tau Board level Signal integrity 1. Mentor HyperLYNX 2. Mentor ICX 3. Cadence Specctraquest "Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message news:91710219.0311050420.679a7a14@posting.google.com...> I meant much more. For a detailed design flow, including code > coverage, DFT, physical synthesis, etc. > > regards, > nagaraj > > Mike Treseler <tres@tc.fluke.com> wrote in messagenews:<3FA83665.9030100@tc.fluke.com>...> > 1. Design entry > > Tool1: emacs vhdl-mode, verilog mode > > Tool2: Quartus block diagram > > 2. Simulation > > Tool1: Modelsim > > Tool2: Aldec > > 3. Synthesis > > Tool1: Leo Spec > > Tool2: Synplify Pro > > Tool3: Quartus > > Tool4: XST > > 4. Place and Route > > Tool1: Xilinx Place & Route + static timing > > Tool2: Quartus Place & Route + static timing > > > > -- Mike Treseler