in the schematic capture of Xilinx ISE, there is ADD symbol button, which will allow you to pick a component by function, IE : AND NAND MUX COUNTER etc... I want to be able to pick a symbol by 74xxxx digital logic series number. add symbol symbol = 7404 etc. Is this an available option? Rich
digital logic library by 74xxxx part number?
Started by ●February 12, 2006
Reply by ●February 12, 20062006-02-12
<aiiadict@gmail.com> wrote in message news:1139778197.131276.257880@g14g2000cwa.googlegroups.com...> in the schematic capture of Xilinx ISE, there > is ADD symbol button, which will allow you to > pick a component by function, IE : > > AND > NAND > MUX > COUNTER > > > etc... > > I want to be able to pick a symbol by 74xxxx digital > logic series number. > > add symbol > symbol = 7404 > > > etc. > > Is this an available option? > > Rich >You certainly can with Altera Quartus. Slurp
Reply by ●February 12, 20062006-02-12
If Xilinx won't do it, what schematic capture will, and it has to output SCH filetype or other Xilinx compatible schematic format. Rich
Reply by ●February 13, 20062006-02-13
Perhaps you can find an earlier version of ISE, say, v5.1, which may, in fact, be the last version that supported functions like that, and the fidelity of reproduction of TTL functions is not 100%, BTW, you can do that with CPLD designs. The TTL components went away in FPGA libraries a release earlier than for CPLD's. The schematic package, ECS, leaves a bit to be desired anyway. It doesn't align components very well, selects components if you click anywhere near them, frequently scrambles your carefully laid-out wires, etc. It also freuquently does stuff you want quite backwards, e.g. numbers signal names in the opposite order from what you told it, but only sometimes, and sometimes requires you to exit the drawing package before it will accept your drawing. A little prune juice, and a lot of whiskey will help a little. Richard
Reply by ●February 13, 20062006-02-13
Hi Rich, in the older Webpacks (ISE 4.2, maybe even 5.x) was a small TTL library available for CPLDs only. Maybe you can access it by the ISE-Classic programms if you have no acess to the older Webpacks. It surely can be converted to FPGAs. But do you really need it? The symbol INV is an Inverter , is called an inverter, and is the only single Inverter. Why use multiple names for the same thing (e.g. 74xx04, 74xx05,74xx14, 74xx4049). All Inverters, some with special features that may be unused inside a programmable chip. Why drawing more than nessecary? AND2b1 and its companions gives you inverted inputs without pushing symbols around. INV4 etc. work on whole busses without need to name every line. The MSI functions don't have all the excessive I/Os that are often unused or abused for "tricks". Designing with the pure functions gives you better results. Some old chips can hardly be reimplemented in CPLDs or FPGAs. Look for 74ls193 in the forums. Time is better spent on rethinking the old design, or even learn a HDL than reimplementing libraries for obsolete components. From your former post I know that you would prefer to do nearly nothing to reimplement your old TTL schematic into actual devices (OSR :-) ) but be sure, it won't work that way. Every beginners pitfall is waiting for you. (multiple and gated clocks, asynchronous and gate delay designs and many more) have a nice synthesis Eilert
Reply by ●February 13, 20062006-02-13
For the most part, I'm right with you on your comments. However ... <sigh> ... there's always a however ... sometimes someone hands you a schematic and says, "THIS is what I want, and THIS is what I'll pay you to recreate in programmable logic," and that's where the fun begins. I've had little trouble getting "transcriptions" of SSI/MSI designs to work in CPLD's, with the exception of one-shots, which can, but shouldn't, be implemented in CPLD's with SCHMITT inputs. However, some "TTL" library parts didn't work quite right when taken directly from the XILINX library, and some had extra or omitted signals, the justification for which was seldom available. If someone wants THIS generated in CPLD/FPGA hardware, you have to give it your best effort, but if you do it in HDL, it's unlikely anybody will be able to review it to their satisfaction. If you present a 100 modules of VHDL to a group of guys my age, who went to college when transistor radios were just becoming commonplace, all you'll get is "what's this?" and maybe fired, unless, say, you can plug our device in an application for what you've got to replace, and demonstrate it works as well as the original. Reviews are a problem. If you have a well-designed, well-documented, fully verified logic design implemented on a device that's working to your satisfaction, you still have to go through the review process. If the senior engineers, and I don't mean those kids who don't even remember back before there was a NASA, are presented with a single-page schematic, they can grasp what's going on in the design, at least to their own satisfaction, with the help of the documentation, in about a half an hour. If you hand them a stack of HDL listings, and especially if you've presented them with a block diagram that represents a bunch of HDL-implemented blocks, you're in for a rough ride, and a week of being raked over the coals, at great expense to someone, since all that engineering horsepower has to be paid, and the buy who signs their checks probably signs yours, too. If you show them a schematic, they know what it means and can interpret it as well as they need. If you substitute synchronous for asynchronous logic, they'll understand why you did that. Support it with block schematics and simulations and they'll bite. If you support it with HDL blocks and simulations, they'll fight. You'll be accused of bait-and-switching on them. That, BTW, is why I'm so upset over the fact that both XILINX and ALTERA have made their schematic capture software a distant, neglected, and indadequately documented stepchild. Richard
Reply by ●February 13, 20062006-02-13
richard wrote:> If > the senior engineers, and I don't mean those kids who don't even > remember back before there was a NASA, are presented with a single-page > schematic, they can grasp what's going on in the design, at least to > their own satisfaction, with the help of the documentation, in about a > half an hour.Good luck fitting a modern design on a single schematic sheet. Unless, of course, that sheet is Z size, or whatever.> That, BTW, is why I'm so upset over the fact that both XILINX and > ALTERA have made their schematic capture software a distant, neglected, > and indadequately documented stepchild.Seems to me that Altera and Xilinx (and Lattice, and Actel and QuickLogic) are putting their efforts where it's needed (and wanted), which is to say in better synthesis tools. -a
Reply by ●February 13, 20062006-02-13
There is an older generation of designers (my generation) who grew up thinking in terms of the 7400 data book: 74161, 74138, etc create instant associations. But we must all realize: those designs were created between 1968 and 1971, i.e. more than 35 years ago, when designers at Fairchild (I was one of them) and T.I. defined practical logic blocks that fit into a 16-pin package, and could be interconnected with a minimum of extra "junk", like inverters. Those "rules of the games" have changed drastically. 16-pin packages have become 300- to 1400-pin packages, inverters have evaporated in the LUT structures... Apparently we did too good a job of indoctrinating the logic designers to think in terms of MSI functions. But remember, this was created for your father's or even grandfather's generation. 35 years is an eternity in this business. Keep thinking in terms of functionality, draw block diagrams, but leave the gory details to the synthesizers. R.I.P. 7400 ! Peter Alfke, Xilinx Applications
Reply by ●February 13, 20062006-02-13
Peter Alfke wrote:> There is an older generation of designers (my generation) who grew up > thinking in terms of the 7400 data book: 74161, 74138, etc create > instant associations.Indeed. Some EE professors are still teaching this abstraction level.> Apparently we did too good a job of indoctrinating the logic designers > to think in terms of MSI functions.Yes. Even some of the newer generation seem convinced that FPGAs are full of little counters, shifters and adders that just waiting to be wired up.> Keep thinking in terms of functionality, draw block diagrams, but leave > the gory details to the synthesizers. R.I.P. 7400 !Well said. Thanks for the posting. -- Mike Treseler
Reply by ●February 14, 20062006-02-14
