SCHEMATICS ... Is anybody as frustrated as I am with the software?

I've recently noticed that the schematic software that's included with
XILINX' ISE WebPack and with Altera's Quartus WebEdition software is
pretty lame.  It looks as though the folks who generate, maintain, and
repair this stuff have never had to make their living with it.

I recently abandoned the last two releases of XILINX' WebPack stuff
because there were problems making it nearly unuseable.  Release 7 was
apparently written in VB or JAVA, hence, was so slow I couldn't use it,
and release 8 was not only slow but "broken" in a number of ways that I
couldn't use it either.

Several bugs that I reported in 2002 still can be found, including a
problem aligning bus taps with nets drawn on the grid that aligns with
the symbol pins, translation/netlist errors, random breakdown in
sequential signal-numbering (tell it to increment, and it decrements,
and vice-versa, but not always) ... I could go on, and will in a note
to the local sales rep ...

The release 3 and 4 of Quartus wouldn't display whole text strings on
any of our HP desktops.  That meant that, for a year, no Altera
development could be done, except with MaxPlus-II.

The current Quartus doesn't associate net names between net segments,
i.e. if I put a right angle in a "wire," it loses its net-name
property.   There are cases wherein a net name can't be deleted from a
sheet, even if the net's gone, where a net name=>pin assignment won't
work because the assignment editor doesn't allow editing of the net
name, and busses ... well ...

So, are any of you guys seeing the same sorts of problems?  Doesn't it
make sense to have a half-hour review of a schematic rather than a
week-long review of a ream of HDL listings?

Richard

richard wrote:
> I've recently noticed that the schematic software that's included with
> XILINX' ISE WebPack and with Altera's Quartus WebEdition software is
> pretty lame.  It looks as though the folks who generate, maintain, and
> repair this stuff have never had to make their living with it.
>
> I recently abandoned the last two releases of XILINX' WebPack stuff
> because there were problems making it nearly unuseable.  Release 7 was
> apparently written in VB or JAVA, hence, was so slow I couldn't use it,
> and release 8 was not only slow but "broken" in a number of ways that I
> couldn't use it either.
>
> Several bugs that I reported in 2002 still can be found, including a
> problem aligning bus taps with nets drawn on the grid that aligns with
> the symbol pins, translation/netlist errors, random breakdown in
> sequential signal-numbering (tell it to increment, and it decrements,
> and vice-versa, but not always) ... I could go on, and will in a note
> to the local sales rep ...
>
> The release 3 and 4 of Quartus wouldn't display whole text strings on
> any of our HP desktops.  That meant that, for a year, no Altera
> development could be done, except with MaxPlus-II.
>
> The current Quartus doesn't associate net names between net segments,
> i.e. if I put a right angle in a "wire," it loses its net-name
> property.   There are cases wherein a net name can't be deleted from a
> sheet, even if the net's gone, where a net name=>pin assignment won't
> work because the assignment editor doesn't allow editing of the net
> name, and busses ... well ...
>
> So, are any of you guys seeing the same sorts of problems?  Doesn't it
> make sense to have a half-hour review of a schematic rather than a
> week-long review of a ream of HDL listings?
>
> Richard

For most of us, the days of schematics are long gone but they still
remain useful for high level views and for floorplanning. The best
schematic tool I ever used was VLSI/Compass for ASIC design, it got
most everything right and even allowed true edit in place of symbols
within a live schematic but VLSI Inc developed that for their ASIC biz
some 20yrs ago. When it garbage collected though it died for 20mins.
Once synthesis & HDLs took over, all these schematic tools went south,
there is no revenue model for them.

My big gripe has been the uselessness of the synthesized schematics
from code, if the code is trivial to understand, the schematics can be
passable but not of much real help. If the code is too complex to
understand, the software has no way to know how to reconstruct a decent
looking schematic. Since these are constructed each & every time from
synthesis, the slightest change to source code means a complete
regeneration of synthesized schematic. Much of the code wouldn't really
translate well to schematics as it looks more like C expression code
than object instances. I would like to see a mechanism where by the
synthesized schematic could be somewhat edited for good presentation
and that the result be reused for the next pass without the tool
getting confused by small changes. The biggest joke is when you build
datapaths n bits wide, and these tools usually just consider these bit
paths as just more soso giving mostly random placements that are easily
made non linear by smaller edge details. If a draftsman created these
machine like schematics, they be out the door pronto. In the ASIC world
they have $$$ software that can take flattened mass of logic with
regular hierarchy removed and refind the natural hierarchy and put it
back in for more regular layout, but that wouldn't work too well over
FPGA fabric. Don't expect too much from unpaid software.

end of rant, 

John Jakson

richard wrote:

> So, are any of you guys seeing the same sorts of problems?  Doesn't it
> make sense to have a half-hour review of a schematic rather than a
> week-long review of a ream of HDL listings?

HDL code is optimized for simulation and synthesis.
It makes more sense to review the simulation waveforms.
because, for the right design rules, the waves will be
the same on the bench.

      -- Mike Treseler

richard wrote:

> So, are any of you guys seeing the same sorts of problems?  Doesn't
> it make sense to have a half-hour review of a schematic rather than a
>  week-long review of a ream of HDL listings?

I was using schematic entry for as much of my design work as possible a 
year or two ago, much to my colleague's dismay!

(I must admit, finding and placing bus joiners and creating new nets 
just to wire up a component that would be 2 lines of VHDL was beginning 
to annoy me.)

However, since then I've been doing a lot more HDL work and have 
actually gone back and converted all my early schematics to VHDL! I'm 
now a "born-again" HDL'ian and find it so much quicker and more 
convenient to develop, maintain, re-use and *PORT* HDL code - not to 
mention source control is a lot nicer/easier now. My testbenches are all 
written in HDL as well now (mainly Verilog).

FWIW, I'd never return to schematics. Yes, top level can be nice as Mike 
pointed out, but I find the disadvantages - slow, buggy tools, 
cumbersome maintenance, no portability - far outweigh the benefits.

Regards,
Mark

Mark McDougall wrote:
> richard wrote:
> 
>> So, are any of you guys seeing the same sorts of problems?  Doesn't
>> it make sense to have a half-hour review of a schematic rather than a
>>  week-long review of a ream of HDL listings?
> 
> 
> I was using schematic entry for as much of my design work as possible a 
> year or two ago, much to my colleague's dismay!
> 
> (I must admit, finding and placing bus joiners and creating new nets 
> just to wire up a component that would be 2 lines of VHDL was beginning 
> to annoy me.)
> 
> However, since then I've been doing a lot more HDL work and have 
> actually gone back and converted all my early schematics to VHDL! I'm 
> now a "born-again" HDL'ian and find it so much quicker and more 
> convenient to develop, maintain, re-use and *PORT* HDL code - not to 
> mention source control is a lot nicer/easier now. My testbenches are all 
> written in HDL as well now (mainly Verilog).
> 
> FWIW, I'd never return to schematics. Yes, top level can be nice as Mike 
> pointed out, but I find the disadvantages - slow, buggy tools, 
> cumbersome maintenance, no portability - far outweigh the benefits.
> 
> Regards,
> Mark

If you could watch the operation of the circuits inside your prototyping board 
directly on your schematics as they run in real-time, or clock by clock would 
you find this useful?

Andrew Ward wrote:
> 
> If you could watch the operation of the circuits inside your prototyping 
> board directly on your schematics as they run in real-time, or clock by 
> clock would you find this useful?

I worked with some tools way back when that had this capability - I 
think Mentor quicksim/design architect IIRC - or maybe it was Daisy. I 
found it to be not really that useful. You really need to see waveforms 
to make sense of what is going on.

Speaking of schematic editors, Mentor's Design Architect was a fantastic 
editor. The "stroke commands" were genius. Hold the middle mouse button 
in and draw little free-hand "glyphs" that would disappear when you 
released the button as a way to invoke common commands like select, 
copy, move, delete etc.

-Jeff

Jeff Cunningham wrote:
> Andrew Ward wrote:
> 
>>
>> If you could watch the operation of the circuits inside your 
>> prototyping board directly on your schematics as they run in 
>> real-time, or clock by clock would you find this useful?
> 
> 
> I worked with some tools way back when that had this capability - I 
> think Mentor quicksim/design architect IIRC - or maybe it was Daisy. I 
> found it to be not really that useful. You really need to see waveforms 
> to make sense of what is going on.
> 

Yes that is what our product does, you can see the values directly on 
components, and as waveforms as well. Best of both worlds, only it is not a 
simulator, what you see is what's going on in the hardware. Here is a picture of 
what I mean:
http://www.hevday.com/operation_pictures.html
If you look at the bottom of this page there is a picture of our long time scale 
waveform view. With this you can watch for spikes etc. over days of real time. 
Can you do that with your simulator?

> Speaking of schematic editors, Mentor's Design Architect was a fantastic 
> editor. The "stroke commands" were genius. Hold the middle mouse button 
> in and draw little free-hand "glyphs" that would disappear when you 
> released the button as a way to invoke common commands like select, 
> copy, move, delete etc.
> 
> -Jeff

"Andrew Ward" <andy.ward@hevday.com> wrote in message 
news:2laIf.146249$vH5.1206909@news.xtra.co.nz...
>
> If you could watch the operation of the circuits inside your prototyping 
> board directly on your schematics as they run in real-time, or clock by 
> clock would you find this useful?

Synplicity sell something called Identify. It shows the operation of the 
circuit in the HDL source, I believe. Uses the JTAG interface. Dunno if it's 
any good, I never make any coding errors, so I don't need it. Ahem! ;-)
http://www.synplicity.com/products/identify/
Personally, I fail to see any benefit of schematics. Once you've been using 
HDLs long enough, it's just as easy to visualise the FFs, gates etc. from 
the code as it is to look at a pictorial representation of them. You can 
also see a lot more of them on one page! Mike's point about simulation 
reviews is spot on, and in my opinion, people who are using schematics would 
be better off following this course rather than reviewing the schematic 
sheets.
I don't want to start a flame war here, this is only my personal preference, 
greatly influenced by the fact that I wasted the best part of an afternoon 
last week when I had to maintain some old viewlogic stuff. Turns out a 
square dot doesn't connect like a round one. The problem was compounded when 
the software engineer solved it. Arse.
Cheers, Syms.
p.s. One last point, it's easy to write Perl scripts to create/change HDLs. 
How you gonna do that with schematics? HDLs also have much more powerful 
reuse capabilities. Generics to control bit widths, blah, blah, blah. This 
schematics vs. HDLs must've been gone over a hundred times on CAF. I'll shut 
up. 

richard wrote:
> I've recently noticed that the schematic software that's included with
> XILINX' ISE WebPack and with Altera's Quartus WebEdition software is
> pretty lame.  It looks as though the folks who generate, maintain, and
> repair this stuff have never had to make their living with it.
>
> I recently abandoned the last two releases of XILINX' WebPack stuff
> because there were problems making it nearly unuseable.  Release 7 was
> apparently written in VB or JAVA, hence, was so slow I couldn't use it,
> and release 8 was not only slow but "broken" in a number of ways that I
> couldn't use it either.
>
> Several bugs that I reported in 2002 still can be found, including a
> problem aligning bus taps with nets drawn on the grid that aligns with
> the symbol pins, translation/netlist errors, random breakdown in
> sequential signal-numbering (tell it to increment, and it decrements,
> and vice-versa, but not always) ... I could go on, and will in a note
> to the local sales rep ...
>
> The release 3 and 4 of Quartus wouldn't display whole text strings on
> any of our HP desktops.  That meant that, for a year, no Altera
> development could be done, except with MaxPlus-II.
>
> The current Quartus doesn't associate net names between net segments,
> i.e. if I put a right angle in a "wire," it loses its net-name
> property.   There are cases wherein a net name can't be deleted from a
> sheet, even if the net's gone, where a net name=>pin assignment won't
> work because the assignment editor doesn't allow editing of the net
> name, and busses ... well ...
>
> So, are any of you guys seeing the same sorts of problems?  Doesn't it
> make sense to have a half-hour review of a schematic rather than a
> week-long review of a ream of HDL listings?
>
> Richard

It was the utter uselessness of the schematic tools for programmable
logic (they sucked 15 years ago too) that helped push me to learn
Verilog and VHDL. I am now far more comfortable using those languages
than schematic entry for programmable designs (although I use schematic
tools for PCB designs, obviously).

I know there are some who have no choice but to maintain old schematic
based programmable designs, but for new designs I would just go to a
synthesis language.

Cheers

PeteS

> 
  Syms, I think the strongest argument for schematics is readability.  I 
still often have to draw out the schematic on an HDL design to fully 
grok what is going on, and I've been pretty much exclusively VHDL since 
aroun 1999.  On the flip-side, the state of the HDL tools makes it much 
easier to reuse.  It can be done with schematics, but the mainstream 
tools didn't do a very good job of supporting it.  Back when I was an 
avid viewlogic user (and maybe a rabid one too), I had more or less 
perfected a system where I got much more reuse than the average bear. 
My schematics were also much more hierarchical than most, with each 
level of a design fitting on one sheet, and the low levels consisting of 
  one and two bit slices.  I could still use a good HDL to schematic 
viewer that allows you to hand edit the position of stuff to make it a 
readable schematic.