I just begining my work on dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs. I have readed those article sur the site of Xilinx e.g; the guild of configuration , use guid etc. but I havent also any idea for the begining. I wish someone can give me a real exemple or some advices for the dynamic partial reconfiguration of Virtex-4. thanks on advance, xun
dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
Started by ●February 14, 2006
Reply by ●February 14, 20062006-02-14
Hi xun, Check out Xilinx's PlanAhead product. Quote:- "New Partial Reconfiguration features and capabilities in PlanAhead 8.1 simplify the implementation of this complex but powerful design flow. Combined with the ISE 8.1i Design Tools, PlanAhead 8.1 delivers the industry's only front-to-back solution for partial reconfiguration." www.xilinx.com/planahead Make sure you report back to let us know how you're getting along! Good luck (you'll need it!) Syms. <zhangxun0501@gmail.com> wrote in message news:1139929097.244112.281090@g44g2000cwa.googlegroups.com...>I just begining my work on dynamic partial reconfiguration of Xilinx > Virtex-4 FPGAs. I have readed those article sur the site of Xilinx > e.g; the guild of configuration , use guid etc. but I havent also any > idea for the begining. I wish someone can give me a real exemple or > some advices for the dynamic partial reconfiguration of Virtex-4. > > thanks on advance, > > xun >
Reply by ●February 14, 20062006-02-14
Partial REconfiguration on Virtex-4 using ISE8.1 doesnt work. Good Luck On 14 Feb 2006 06:58:17 -0800, zhangxun0501@gmail.com wrote:>I just begining my work on dynamic partial reconfiguration of Xilinx >Virtex-4 FPGAs. I have readed those article sur the site of Xilinx >e.g; the guild of configuration , use guid etc. but I havent also any >idea for the begining. I wish someone can give me a real exemple or >some advices for the dynamic partial reconfiguration of Virtex-4. > >thanks on advance, > >xun
Reply by ●February 14, 20062006-02-14
I recommend reading the article below: http://www.fpgajournal.com/articles_2006/20060207_cray.htm Apparently RC works... Peter Alfke
Reply by ●February 14, 20062006-02-14
Partial reconfig for V4 requires additional software that is not included in 8.1i. PlanAhead is also required. You need to contact your local FAE to gain access to this software. Steve Symon wrote:> Hi xun, > Check out Xilinx's PlanAhead product. Quote:- > "New Partial Reconfiguration features and capabilities in PlanAhead 8.1 > simplify the implementation of this complex but powerful design flow. > Combined with the ISE 8.1i Design Tools, PlanAhead 8.1 delivers the > industry's only front-to-back solution for partial reconfiguration." > www.xilinx.com/planahead > Make sure you report back to let us know how you're getting along! > Good luck (you'll need it!) Syms. > > <zhangxun0501@gmail.com> wrote in message > news:1139929097.244112.281090@g44g2000cwa.googlegroups.com... > >>I just begining my work on dynamic partial reconfiguration of Xilinx >>Virtex-4 FPGAs. I have readed those article sur the site of Xilinx >>e.g; the guild of configuration , use guid etc. but I havent also any >>idea for the begining. I wish someone can give me a real exemple or >>some advices for the dynamic partial reconfiguration of Virtex-4. >> >>thanks on advance, >> >>xun >> > > >
Reply by ●February 15, 20062006-02-15
Peter, there is no evidence of _dynamic_ reconfiguration in this article. Actually, Smith-Waterman algorithm is not a good candidate for demonstrating dynamicity, because the query sequence occupies only an edge of the accelerator array => programming a long register is ok. Changing algorithm coefficients would benefit from DPR, but actually, biologists never do so! Xilinx paper "Gene Matching using JBits" in FPL 2002 was an implementation of the Needleman-Wunsch algorithm (simpler than S-W); it also uses a run-time query, and implementation is optimized for given coefficients, so it's not clearly taking advantage of DPR. Anyway JBits was demonstrated to work. Stephane Peter Alfke wrote:> I recommend reading the article below: > > http://www.fpgajournal.com/articles_2006/20060207_cray.htm > > Apparently RC works... > Peter Alfke >
Reply by ●February 15, 20062006-02-15
Of course it works. Self-Reconfiguration on Virtex2,Spartan2 and Spartan3 works fine. I said that Partial Reconfiguration on Virtex4 using ISE doesnt work. I dont know if using PlanAhead it works. We have made many experiments and using Virtex4 during the final assembly phase it fails due to problem with the disabled DCMs, and many global logic that appears during this phase. That global logic goes from TIE elements to CE inputs of the registers inside the slices. For smal designs we have route it manually and we've got some simple design of PR on Virtex4, but for larger designs is imposible to route that logic. Appart for it there are a problem about using Virtex4 block rams in modular design, I reported it, and it supposed to be solved in a IP update for ISE8.1. I havent test it yet. Yesterday, when I downloaded SP2 for ISE8.1 I tested again the designs and the problem of the global logic and unconnected DCMs havent disappear. Regards Javier On 14 Feb 2006 14:16:00 -0800, "Peter Alfke" <peter@xilinx.com> wrote:>I recommend reading the article below: > >http://www.fpgajournal.com/articles_2006/20060207_cray.htm > >Apparently RC works... >Peter Alfke
Reply by ●March 1, 20062006-03-01
The Virtex4 hardware supports partial reconfiguration and includes a lot of special hooks intended to increase the flexibility of usage of Partial Reconfig. Unfortunately the tools haven't quite caught up yet. This should improve with the new Plan Ahead 8.1 and future Software releases. Some applications like Software Defined Radio and Reconfigurable Computing are driving this. If you run into a problem please call the hotline or file a CR. If Partial Reconfig is important to you - let your local FAE know. That way in the future the software and tool support for Partial Reconfiguration will get the priority it deserves. - Vic Javier Castillo wrote:> Of course it works. Self-Reconfiguration on Virtex2,Spartan2 and > Spartan3 works fine. I said that Partial Reconfiguration on Virtex4 > using ISE doesnt work. I dont know if using PlanAhead it works. > > We have made many experiments and using Virtex4 during the final > assembly phase it fails due to problem with the disabled DCMs, and > many global logic that appears during this phase. That global logic > goes from TIE elements to CE inputs of the registers inside the > slices. For smal designs we have route it manually and we've got some > simple design of PR on Virtex4, but for larger designs is imposible to > route that logic. Appart for it there are a problem about using > Virtex4 block rams in modular design, I reported it, and it supposed > to be solved in a IP update for ISE8.1. I havent test it yet. > > Yesterday, when I downloaded SP2 for ISE8.1 I tested again the designs > and the problem of the global logic and unconnected DCMs havent > disappear. > > Regards > > Javier > > On 14 Feb 2006 14:16:00 -0800, "Peter Alfke" <peter@xilinx.com> wrote: > > >>I recommend reading the article below: >> >>http://www.fpgajournal.com/articles_2006/20060207_cray.htm >> >>Apparently RC works... >>Peter Alfke
Reply by ●March 2, 20062006-03-02
Hi Xun, Planahead 8.1 supports partial reconfiguration in Virtex 4. Check out this recent article: http://www.us.design-reuse.com/news/news12519.html -Love http://www.ics.uci.edu/~lsinghal
Reply by ●March 2, 20062006-03-02
"Love Singhal" <lovesinghal@gmail.com> wrote in message news:1141290150.815684.165950@v46g2000cwv.googlegroups.com...> Hi Xun, > Planahead 8.1 supports partial reconfiguration in Virtex 4. > Check out this recent article: > http://www.us.design-reuse.com/news/news12519.html > > -Love > http://www.ics.uci.edu/~lsinghal >Hi Singhal, has the partial reconfig evolved since last time the Virtex 2 nightmare? I did partial reconfig with V2 FPGAs, and it was really buggy and inflexible.
