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CPLD-SPI_flash configuration system problem.

Started by mughat February 16, 2006
I have a problem width my CPLD-SPI_flash configuration system.

I have made a configuration interface for my Spartan 3 FPGA involving a CPLD 
(CoolRunner 2) and SPI flash (M25P32).

My FPGA is set up to serial master configuration mode. The FPGA is 
generating the clock for the CPLD and the CPLD transfers the data from the 
SPI flash to the DIN pin on the FPGA. I use the application notes and source 
code xapp800 from Xilinx.

I monitor the CPLD and it steps through states (1-4):
1 STATE_RESET
2 LOAD_READ_OPCODE
3 LOAD_READ_ADDRESS
4 READ_DATA
5 WAIT_STATE

The CPLD stays in state 4 where it waits for the FPGA to indicate 
configuration done by pulling the DONE pin high.

The hardware seams to work. I can see the data on the DIN pin of the FPGA 
but the FPGA never indicates configuration done by pulling the DONE pin 
high.

I think the problem may be the process of converting the .bit file to a 
format that can be written to the serial flash.

Anyone that have any suggestions on how to find the problem?

Andreas Beier
Computer Systems Engineer 


mughat wrote:
> I have a problem width my CPLD-SPI_flash configuration system. > > I have made a configuration interface for my Spartan 3 FPGA involving a CPLD > (CoolRunner 2) and SPI flash (M25P32). > > My FPGA is set up to serial master configuration mode. The FPGA is > generating the clock for the CPLD and the CPLD transfers the data from the > SPI flash to the DIN pin on the FPGA. I use the application notes and source > code xapp800 from Xilinx. > > I monitor the CPLD and it steps through states (1-4): > 1 STATE_RESET > 2 LOAD_READ_OPCODE > 3 LOAD_READ_ADDRESS > 4 READ_DATA > 5 WAIT_STATE > > The CPLD stays in state 4 where it waits for the FPGA to indicate > configuration done by pulling the DONE pin high. > > The hardware seams to work. I can see the data on the DIN pin of the FPGA > but the FPGA never indicates configuration done by pulling the DONE pin > high. > > I think the problem may be the process of converting the .bit file to a > format that can be written to the serial flash. > > Anyone that have any suggestions on how to find the problem?
The first thing I always check is the bit order within bytes. Make sure the SPI isn't swapping your bits, or try swapping bits when you create the SPI flash image.
> > Andreas Beier > Computer Systems Engineer
Do you use any special software tools for reading the .bit file and flash 
image?

"Gabor" <gabor@alacron.com> wrote in message 
news:1140108297.431410.245210@z14g2000cwz.googlegroups.com...
> > mughat wrote: >> I have a problem width my CPLD-SPI_flash configuration system. >> >> I have made a configuration interface for my Spartan 3 FPGA involving a >> CPLD >> (CoolRunner 2) and SPI flash (M25P32). >> >> My FPGA is set up to serial master configuration mode. The FPGA is >> generating the clock for the CPLD and the CPLD transfers the data from >> the >> SPI flash to the DIN pin on the FPGA. I use the application notes and >> source >> code xapp800 from Xilinx. >> >> I monitor the CPLD and it steps through states (1-4): >> 1 STATE_RESET >> 2 LOAD_READ_OPCODE >> 3 LOAD_READ_ADDRESS >> 4 READ_DATA >> 5 WAIT_STATE >> >> The CPLD stays in state 4 where it waits for the FPGA to indicate >> configuration done by pulling the DONE pin high. >> >> The hardware seams to work. I can see the data on the DIN pin of the FPGA >> but the FPGA never indicates configuration done by pulling the DONE pin >> high. >> >> I think the problem may be the process of converting the .bit file to a >> format that can be written to the serial flash. >> >> Anyone that have any suggestions on how to find the problem? > > The first thing I always check is the bit order within bytes. Make > sure the SPI isn't swapping your bits, or try swapping bits when you > create the SPI flash image. > >> >> Andreas Beier >> Computer Systems Engineer >
I don't usually use the .bit file directly.  I use Impact to generate a
PROM file in HEX format (or use promgen if you prefer a command
line interface).  This is a very simple format with just the bitstream
and no header.  Then I use a simple C program to turn this back
into binary for storage in flash.

Impact or promgen gives you the choice of swapped or not swapped
bits when generating the .hex file.  Then if your embedded firmware
gets the bit order wrong, you can just re-build the .hex file using
the opposite swap mode rather than changing the firmware.

A note of warning.  Impact 8.1i sp1 (and maybe sp2?) GUI always
sets the swap bits mode when generating .hex files, so you need
to run promgen from the command line to generate unswapped
.hex files.

mughat wrote:
> Do you use any special software tools for reading the .bit file and flash > image? > > "Gabor" <gabor@alacron.com> wrote in message > news:1140108297.431410.245210@z14g2000cwz.googlegroups.com... > > > > mughat wrote: > >> I have a problem width my CPLD-SPI_flash configuration system. > >> > >> I have made a configuration interface for my Spartan 3 FPGA involving a > >> CPLD > >> (CoolRunner 2) and SPI flash (M25P32). > >> > >> My FPGA is set up to serial master configuration mode. The FPGA is > >> generating the clock for the CPLD and the CPLD transfers the data from > >> the > >> SPI flash to the DIN pin on the FPGA. I use the application notes and > >> source > >> code xapp800 from Xilinx. > >> > >> I monitor the CPLD and it steps through states (1-4): > >> 1 STATE_RESET > >> 2 LOAD_READ_OPCODE > >> 3 LOAD_READ_ADDRESS > >> 4 READ_DATA > >> 5 WAIT_STATE > >> > >> The CPLD stays in state 4 where it waits for the FPGA to indicate > >> configuration done by pulling the DONE pin high. > >> > >> The hardware seams to work. I can see the data on the DIN pin of the FPGA > >> but the FPGA never indicates configuration done by pulling the DONE pin > >> high. > >> > >> I think the problem may be the process of converting the .bit file to a > >> format that can be written to the serial flash. > >> > >> Anyone that have any suggestions on how to find the problem? > > > > The first thing I always check is the bit order within bytes. Make > > sure the SPI isn't swapping your bits, or try swapping bits when you > > create the SPI flash image. > > > >> > >> Andreas Beier > >> Computer Systems Engineer > >