Here is some code showing a problem I am having with Quartus. Seems
using a type cast with an aggregate throws it all off. This is just a
simple test case which uses a 16 bit bidir bus to write to an 8 bit
register and read it back.
-- VHDL created by Rick Collins
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
ENTITY Test1 is
PORT (
Data : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);
Addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
CSN : IN STD_LOGIC;
RDN : IN STD_LOGIC;
WRN : IN STD_LOGIC;
LED : OUT STD_LOGIC;
Reset : IN STD_LOGIC;
SysClk : IN STD_LOGIC); -- 50 MHz Clock
END Test1;
ARCHITECTURE behavior OF Test1 IS
constant SysClkRate : real := 50000.0; -- Rate in KHz
signal ScratchReg : STD_LOGIC_VECTOR (7 downto 0);
signal DataOut : STD_LOGIC_VECTOR (15 downto 0);
signal ReadScratchReg : STD_LOGIC;
BEGIN
ReadScratchReg <= (not RDN) WHEN (Addr="00001000") and (CSN='0')
ELSE '0';
-- VERSION 1
-- These lines work correctly
-- Data (15 downto 8) <= (others => '0') WHEN (ReadScratchReg = '1')
-- ELSE (others => 'Z');
-- Data (7 downto 0) <= ScratchReg WHEN (ReadScratchReg = '1')
-- ELSE (others => 'Z');
-- VERSION 2
-- This line fails by disabling the tristate buffers
-- Data <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') &
ScratchReg WHEN (ReadScratchReg = '1')
-- ELSE (others => 'Z');
-- The difference seems to be the use of the type cast.
-- Using a type cast with the (others => aggregate seems to fail in
other cases as well.
-- VERSION 3
-- This version produces open drain outputs
Data <= DataOut WHEN (ReadScratchReg = '1')
ELSE (others => 'Z');
-- This seems to work ok
-- DataOut <= "00000000" & ScratchReg;
-- This produces no register and open drain drivers
DataOut <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') &
ScratchReg;
ScratchRegister: process (SysClk, Reset) begin
if (Reset = '1') then
ScratchReg <= (others => '0');
elsif (rising_edge(SysClk)) then
if (Addr = "00001000") THEN
if (WRN = '0' and CSN = '0') THEN
ScratchReg <= Data (7 downto 0);
end if;
end if;
end if;
end process ScratchRegister;
LED <= ScratchReg(0) AND ReadScratchReg;
END behavior;
As seen under VERSION 3, using the type cast on an aggregate produces a
design with the register not driving the bidir output pins. I don't see
any messages saying the registers were deleted, but the only bit that
remains is the zero bit which drives the LED output. All of the DataOut
nets are listed as undriven and tied to ground.
Using a fixed size vector seems to work ok. It also works ok if I
separate the two halves of the bus and don't use a type cast on the
aggregates. Is this a Quartus bug?
I tried contacting Altera support, but after waiting on hold to talk to
someone, I got put on hold again and then cut off.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Quartus VHDL problem with aggregate and type cast
Started by ●July 11, 2003
Reply by ●July 14, 20032003-07-14
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F0F337C.27A8ED76@yahoo.com... <snip>> -- VERSION 1 > -- These lines work correctly > -- Data (15 downto 8) <= (others => '0') WHEN (ReadScratchReg ='1')> -- ELSE (others => 'Z'); > -- Data (7 downto 0) <= ScratchReg WHEN (ReadScratchReg = '1') > -- ELSE (others => 'Z'); > > -- VERSION 2 > -- This line fails by disabling the tristate buffers > -- Data <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') & > ScratchReg WHEN (ReadScratchReg = '1') > -- ELSE (others => 'Z'); > -- The difference seems to be the use of the type cast. > -- Using a type cast with the (others => aggregate seems to fail in > other cases as well. > > -- VERSION 3 > -- This version produces open drain outputs > Data <= DataOut WHEN (ReadScratchReg = '1') > ELSE (others => 'Z'); > -- This seems to work ok > -- DataOut <= "00000000" & ScratchReg; > -- This produces no register and open drain drivers > DataOut <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') & > ScratchReg; >Hallo Rick, just out of curiosity, have you tried using a named subtype? E.g. architecture... subtype vec8 is std_logic_vector(7 downto 0); begin ... -- VERSION 3 -- This version produces open drain outputs Data <= DataOut WHEN (ReadScratchReg = '1') ELSE (others => 'Z'); -- This seems to work ok -- DataOut <= "00000000" & ScratchReg; -- This produces no register and open drain drivers DataOut <= Vec8'(others => '0') & ScratchReg; I wondered if Quartus is getting confused by the (15 downto 8) slice? The reason I'm asking is that by using STD_LOGIC_VECTOR(15 downto 8) you create an anonymous subtype, and I know that anonymous subtypes are not always allowed where named subtypes are allowed. For instance, it's illegal to declare a function returning an anonymous subtype, but it's OK with a named subtype. regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
Reply by ●July 14, 20032003-07-14
Alan Fitch wrote:> > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3F0F337C.27A8ED76@yahoo.com... > <snip> > > -- VERSION 1 > > -- These lines work correctly > > -- Data (15 downto 8) <= (others => '0') WHEN (ReadScratchReg = > '1') > > -- ELSE (others => 'Z'); > > -- Data (7 downto 0) <= ScratchReg WHEN (ReadScratchReg = '1') > > -- ELSE (others => 'Z'); > > > > -- VERSION 2 > > -- This line fails by disabling the tristate buffers > > -- Data <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') & > > ScratchReg WHEN (ReadScratchReg = '1') > > -- ELSE (others => 'Z'); > > -- The difference seems to be the use of the type cast. > > -- Using a type cast with the (others => aggregate seems to fail in > > other cases as well. > > > > -- VERSION 3 > > -- This version produces open drain outputs > > Data <= DataOut WHEN (ReadScratchReg = '1') > > ELSE (others => 'Z'); > > -- This seems to work ok > > -- DataOut <= "00000000" & ScratchReg; > > -- This produces no register and open drain drivers > > DataOut <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') & > > ScratchReg; > > > > Hallo Rick, > just out of curiosity, have you tried using a named > subtype? > E.g. > > architecture... > subtype vec8 is std_logic_vector(7 downto 0); > begin > > ... > > -- VERSION 3 > -- This version produces open drain outputs > Data <= DataOut WHEN (ReadScratchReg = '1') > ELSE (others => 'Z'); > -- This seems to work ok > -- DataOut <= "00000000" & ScratchReg; > -- This produces no register and open drain drivers > DataOut <= Vec8'(others => '0') & ScratchReg; > > I wondered if Quartus is getting confused by the (15 downto 8) slice? > > The reason I'm asking is that by using STD_LOGIC_VECTOR(15 downto 8) > you create an anonymous subtype, and I know that anonymous subtypes > are not always allowed where named subtypes are allowed. For instance, > it's illegal to declare a function returning an anonymous subtype, > but it's OK with a named subtype. > > regards > > AlanAlan, yes, that worked. Is this a bug that I should report to Altera? Or is this to be expected in VHDL? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●July 15, 20032003-07-15
rickman wrote:> > Alan Fitch wrote: > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:3F0F337C.27A8ED76@yahoo.com... > > <snip> > > > -- VERSION 1 > > > -- These lines work correctly > > > -- Data (15 downto 8) <= (others => '0') WHEN (ReadScratchReg = > > '1') > > > -- ELSE (others => 'Z'); > > > -- Data (7 downto 0) <= ScratchReg WHEN (ReadScratchReg = '1') > > > -- ELSE (others => 'Z'); > > > > > > -- VERSION 2 > > > -- This line fails by disabling the tristate buffers > > > -- Data <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') & > > > ScratchReg WHEN (ReadScratchReg = '1') > > > -- ELSE (others => 'Z'); > > > -- The difference seems to be the use of the type cast. > > > -- Using a type cast with the (others => aggregate seems to fail in > > > other cases as well. > > > > > > -- VERSION 3 > > > -- This version produces open drain outputs > > > Data <= DataOut WHEN (ReadScratchReg = '1') > > > ELSE (others => 'Z'); > > > -- This seems to work ok > > > -- DataOut <= "00000000" & ScratchReg; > > > -- This produces no register and open drain drivers > > > DataOut <= STD_LOGIC_VECTOR (15 downto 8)'(others => '0') & > > > ScratchReg; > > > > > > > Hallo Rick, > > just out of curiosity, have you tried using a named > > subtype? > > E.g. > > > > architecture... > > subtype vec8 is std_logic_vector(7 downto 0); > > begin > > > > ... > > > > -- VERSION 3 > > -- This version produces open drain outputs > > Data <= DataOut WHEN (ReadScratchReg = '1') > > ELSE (others => 'Z'); > > -- This seems to work ok > > -- DataOut <= "00000000" & ScratchReg; > > -- This produces no register and open drain drivers > > DataOut <= Vec8'(others => '0') & ScratchReg; > > > > I wondered if Quartus is getting confused by the (15 downto 8) slice? > > > > The reason I'm asking is that by using STD_LOGIC_VECTOR(15 downto 8) > > you create an anonymous subtype, and I know that anonymous subtypes > > are not always allowed where named subtypes are allowed. For instance, > > it's illegal to declare a function returning an anonymous subtype, > > but it's OK with a named subtype. > > > > regards > > > > Alan > > Alan, yes, that worked. Is this a bug that I should report to Altera? > Or is this to be expected in VHDL?To answer my own question, I heard back from Altera today that it is invalid syntax under VHDL, but not providing an error message is an Altera bug. So they should be telling me to not use this syntax and I need to use a named type here. The actual illegal syntax is the range in the type cast. Is that what you meant be anonymous subtype? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
