VirtexII routing data widths

This might be a dumb question, but I can't seem to find it in the Xilinx 
documentation anywhere. I'm using a VirtexII (XC2V2000) FPGA for my 
university project, and can't find out how wide the various 
interconnects between the logic blocks are (i.e. single bit, 4-bit, or 
larger). I understand the hierarchy of it, just not how wide they are... 
anyone got any clues on where I can find this out?

The lines I'm looking at are:

Long lines
Hex lines
Double lines
Direct connect lines

Thanks in advance, and any help is very much appreciated!

Chris

all lines are 'single' line :)
the best info is to look with FPGA editor or then XDL file

Antti wrote:
> all lines are 'single' line :)
> the best info is to look with FPGA editor or then XDL file

Cheers!

Hi (again!)

As we're still looking at this device on quite a low level (we're trying 
to look at implementing a model of neurons in the brain on the device, 
and in particular the connectivity) we've come across another problem in 
our understanding...

When looking at the 'Hierarchical Routing Resources', the paragraph 
states "... a number of resources counted between any two adjacent 
switch matrix rows or columns.". Therefore, are we right in thinking 
that in our device (which has 56x48 CLBs) for the '40 horizontal double 
lines', from each row we can send out 40 connections (giving a total of 
40x48 double connections), or is there something we've missed (as 
depending on which way we look at it, it's either *loads* of 
connections, or *very* few connections!). The same goes for the long 
lines and hex lines etc.

Again, any pointers to documentation would be appreciated, or if someone 
has the time to type a concise answer all the better (the reason we're 
posting is because we can't find anything helpful, so we're hoping to 
learn from your experience, rather than just leeching off you!) :)

Thanks again
Chris

Chris,

Have you looked at the device in FPGA_Editor?

You should.

Austin

Chris Francis wrote:

> Hi (again!)
> 
> As we're still looking at this device on quite a low level (we're trying 
> to look at implementing a model of neurons in the brain on the device, 
> and in particular the connectivity) we've come across another problem in 
> our understanding...
> 
> When looking at the 'Hierarchical Routing Resources', the paragraph 
> states "... a number of resources counted between any two adjacent 
> switch matrix rows or columns.". Therefore, are we right in thinking 
> that in our device (which has 56x48 CLBs) for the '40 horizontal double 
> lines', from each row we can send out 40 connections (giving a total of 
> 40x48 double connections), or is there something we've missed (as 
> depending on which way we look at it, it's either *loads* of 
> connections, or *very* few connections!). The same goes for the long 
> lines and hex lines etc.
> 
> Again, any pointers to documentation would be appreciated, or if someone 
> has the time to type a concise answer all the better (the reason we're 
> posting is because we can't find anything helpful, so we're hoping to 
> learn from your experience, rather than just leeching off you!) :)
> 
> Thanks again
> Chris

Austin Lesea wrote:
> Chris,
>
> Have you looked at the device in FPGA_Editor?
>
> You should.

It would be nice if the fpga editor would allow you to start it without
a design loaded, select the device that you want to explore/edit/design
with, go into edit mode, and save the resulting design from the editing
(if any). Or open an existing design, and be able to extend it by
editing iob's and slices that do not have design elements loaded. ...
but that is another point ...

>From the posters second question, it's likely he's not familar with how
to operate fpga editor.

Actually just looking at it probably will not answer his question, as
the defaults don't show you very much. He needs to get close in, turn
on all the resources (as many are turned off to reduce the visual
clutter), and put it in edit mode. IE from the tool bar, where the
yellow controls are:

1) turn on local lines

2) turn on long lines

3) turn on pin wires

4) turn on Pips

5) turn on switch boxes

Then from the loaded design, select a site entry from list 1, click on
the red find tool to zoom in on it, then zoom out one or two steps and
look around that are in detail.

start clicking on the circles at the edges of the switch boxes to see
the connection resources available, and open up the clb and iob blocks
that have design elements to see the internal connections.

toys,

Open FPGA_Editor.  Start a new project for a part.  Add nothing (or 
maybe an output pin that drives a '1').

Write out the .ncd.  That is the 'empty' design, with all rules checked 
and met.

Start from there.

Austin

fpga_toys@yahoo.com wrote:

> Austin Lesea wrote:
> 
>>Chris,
>>
>>Have you looked at the device in FPGA_Editor?
>>
>>You should.
> 
> 
> It would be nice if the fpga editor would allow you to start it without
> a design loaded, select the device that you want to explore/edit/design
> with, go into edit mode, and save the resulting design from the editing
> (if any). Or open an existing design, and be able to extend it by
> editing iob's and slices that do not have design elements loaded. ...
> but that is another point ...
> 
>>From the posters second question, it's likely he's not familar with how
> to operate fpga editor.
> 
> Actually just looking at it probably will not answer his question, as
> the defaults don't show you very much. He needs to get close in, turn
> on all the resources (as many are turned off to reduce the visual
> clutter), and put it in edit mode. IE from the tool bar, where the
> yellow controls are:
> 
> 1) turn on local lines
> 
> 2) turn on long lines
> 
> 3) turn on pin wires
> 
> 4) turn on Pips
> 
> 5) turn on switch boxes
> 
> Then from the loaded design, select a site entry from list 1, click on
> the red find tool to zoom in on it, then zoom out one or two steps and
> look around that are in detail.
> 
> start clicking on the circles at the edges of the switch boxes to see
> the connection resources available, and open up the clb and iob blocks
> that have design elements to see the internal connections.
> 

Austin Lesea wrote:
> toys,
>
> Open FPGA_Editor.  Start a new project for a part.  Add nothing (or
> maybe an output pin that drives a '1').
>
> Write out the .ncd.  That is the 'empty' design, with all rules checked
> and met.
>
> Start from there.
>
> Austin

Maybe that's fixed in current release .... I just get:

/home/jbass/bin/fpga_editor: line 5: 26156 Segmentation fault
/raid/xilinx/bin/lin/fpga_editor $*

fpga_toys@yahoo.com wrote:
> Maybe that's fixed in current release .... I just get:
>
> /home/jbass/bin/fpga_editor: line 5: 26156 Segmentation fault
> /raid/xilinx/bin/lin/fpga_editor $*

If that were an open source tool, I would open it in the source code
debugger, fix the bug, and a few minutes or few hours later, actually
experience a tool that doesn't crap out on something that is'nt
mainstream everybody uses it feature.

toys,

Do you have a case number?

Austin

fpga_toys@yahoo.com wrote:

> Austin Lesea wrote:
> 
>>toys,
>>
>>Open FPGA_Editor.  Start a new project for a part.  Add nothing (or
>>maybe an output pin that drives a '1').
>>
>>Write out the .ncd.  That is the 'empty' design, with all rules checked
>>and met.
>>
>>Start from there.
>>
>>Austin
> 
> 
> Maybe that's fixed in current release .... I just get:
> 
> /home/jbass/bin/fpga_editor: line 5: 26156 Segmentation fault
> /raid/xilinx/bin/lin/fpga_editor $*
>