How do I make dual-port RAM from single port RAM?

Hi, there:

In my application, a RAM needs to be written/read from two sets of 
data/address ports
simultaneously. However, in the ASIC library I can only instantiate some 
single port RAM
and RAM which can be written in one port and read from the other port.

How shall I solve this problem?

Thank you.

> In my application, a RAM needs to be written/read from two sets of 
> data/address ports simultaneously. 

estimate your worst case data rates and take a ram with
the sum of these data-rates (plus overhead) ...

then you need to build some logic to switch between
Port A and B to transfer concurrent access to a
sequential access scheme


bye,
Michael

Frank @ CN wrote:
> Hi, there:
> 
> In my application, a RAM needs to be written/read from two sets of 
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some 
> single port RAM
> and RAM which can be written in one port and read from the other port.
> 
> How shall I solve this problem?
> 
> Thank you.

You might get a better idea of the particulars by looking at a data 
sheet for IDT dual-port memories.  (www.idt.com)

For some applications 2 Srams can be used in an alternate buffer
configuration. I assume your 2 ports have similar issue rates otherwise
you may have to mux in time.

Frank, you posted this in the FPGA newsgroup.
In FPGAs, most RAM structures are naturally dual-ported, e.g. the
Virtex BlockRAMs.
You get two ports, whether you asked for it or not!
Peter Alfke, Xilinx Applications.

Frank @ CN wrote:
> Hi, there:
>
> In my application, a RAM needs to be written/read from two sets of
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some
> single port RAM
> and RAM which can be written in one port and read from the other port.
> 
> How shall I solve this problem?
> 
> Thank you.

For dual read ports and a single write port, this is easy.  You just
use two RAMs and always write to both of them together, but read from
them separately, with each treated as a separate read port.  For dual
write ports, it gets a lot harder.

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1141144187.181979.144900@e56g2000cwe.googlegroups.com...
> Frank, you posted this in the FPGA newsgroup.
> In FPGAs, most RAM structures are naturally dual-ported, e.g. the
> Virtex BlockRAMs.
> You get two ports, whether you asked for it or not!
> Peter Alfke, Xilinx Applications.
>

Yeah, the original codes are designed with Xilinx DPRAM with a functional 
testbenches,
now I need to convert the codes into ASIC implementation. The tougher part 
of it is, I
have little understanding of the functionality of the design.

<sharp@cadence.com> wrote in message 
news:1141166824.018412.3910@j33g2000cwa.googlegroups.com...
> For dual read ports and a single write port, this is easy.  You just
> use two RAMs and always write to both of them together, but read from
> them separately, with each treated as a separate read port.  For dual
> write ports, it gets a lot harder.
>

Yeah, there are RAMs in the ASIC library supporting dual read/single write.
I need to make dual read/write out of it. How can I do it now?

Thanks.

As someone else suggested, you could time-multiplex the two ports,
which will take a double-speed clock and extra logic for the
multiplexing.  And this assumes that you are treating this as a
synchronous RAM.

And someone else suggested that you look at your application and see
whether you really need a full dual-port RAM, or whether you are
dealing with a special case where you can segregate it into independent
parts.

You could build the memory from multiple smaller RAMs and add decode
logic to allow you to do two writes, as long as the writes were to
separate RAMs.  If they weren't, one of them would have to wait until
the next cycle.  This requires that the other logic trying to do the
write be able to wait if the memory was "busy".  Note that real
dual-port memories are effectively implemented this way, except that
the RAM granularity is a single word in the memory.  The designers of
those have the advantage that they are designing all the decode logic,
down to the word level.

You can reduce the chance of collisions in this scheme by choosing
which address bits select a RAM and which ones select a word in the
RAM, if you know something about the likely access patterns.  For
example, it may be more likely that two memory writes are going to the
same half of the memory than that they are both going to even (or odd)
addresses.

If you can't multiplex, and can't deal with collisions, then you are
out of luck.  If you want to use predefined RAMs with their predefined
single-port decoding logic, then you are stuck.  Getting true dual-port
requires specialized decode logic in the RAM.

Sounds like a powerful FPGA argument:
Ifyou really need a true dual-port memory (read and write from either
or both ports simultaneously), you are out-of-luck in the ASIC world,
but you can do this just fine in FPGAs.
Nice to know we have such an edge...
Peter Alfke, Xilinx