How do I make dual-port RAM from single port RAM?

"Frank @ CN" <Frank@Frank.com> skrev i meddelandet 
news:du1a67$9g1$1@reader01.singnet.com.sg...
> Hi, there:
>
> In my application, a RAM needs to be written/read from two sets of 
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some 
> single port RAM
> and RAM which can be written in one port and read from the other port.
>
> How shall I solve this problem?
>
> Thank you.
>
>


You can instantiate FOUR rams and implement a valid bit for each location in 
a register.
PortA can write to RAM0,RAM1 and read from RAM0 and RAM2
PortB can write to RAM2,RAM3 and read from RAM1 and RAM3

When PortA writes to address position 17, both RAM0[17] and RAM1[17] are 
updated and the
VALID_BIT[17] is set to 0 indicating that RAM0,1 are valid instead of 
RAM2,3.

When PortB reads address position 17, both RAM1 and RAM3 are read.
A multiplexer on the output is controlled by the selected VALID_BIT,
and since VALID_BIT[17] is zero, it will select the output of RAM1 over 
RAM3.

Obviously this is going to use some gates,so it is not practical for large 
SRAMs.
Running the RAM at 2 x frequency is going to cost a lot less.




-- 
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may bot be shared by my employer Atmel Nordic AB 

So if you are back porting from FPGA to ASIC something stands out right
away which makes this even more messy. Your logic & wiring paths will
now gain significantly in performance but a comparable DPRAM is similar
in performance between ASIC and FPGA for same feature and memory sizes
since they are the same thing (almost). Perhaps there is an option to
double up processing on the logic side rather than try to double up on
SPRAM side.

At this point I can only suggest before continuing with the ASIC, redo
the FPGA design so that it also only uses 1 port atleast you don't burn
masks, tie your hand behind your back on the cheap. Then it should be
easier to convert, atleast you can prove the redesign before
conversion.

Your other option if you really really must use 2 concurrent writes
with no other possibility is to go and get a DP WW RAM core from one of
the ASIC IP houses, Mentor, Cadence, Synopsys and a couple of others
come to mind, not sure who has which. I thought most of the asian
foundries would include such blocks in their library, otherwise it
seems you have a limited library.

So what is the application, & size of DP WW RAM ?

John

The reason I ask for DP WW size is that for applications in say DSP and
data buffering, the memory size might be large but there are possible
options in architecture.

In say a cpu datapath design with a N way ported register file the
options may be far fewer but the size may be much smaller and ameniable
to brute force as suggested by the 4 way Ulf design. That probably
requires that a DP WW store stiil needs to be built but only for 1 bit
direction flag and to the granularity of words or super words if I
understand it right.

John

I just converted a quad port 2r2w to F/Fs this morning; luckily, it
was easy to simplify. You don't give enough info - are the clocks
related? How big is it? Do you have higher frequency clocks available?

Curious that you should have a library with no 2rw memories in it. Can
you tell us whose it is? It sounds like it may too new to be usable.

Sean

I've been trying to follow your problem and now have time to lend some
help. I'm going to approach this from a black-box design point of view.


First question is how are in implementing it or what language are you
using (VHDL, Verilog or something else)?

What size device are you looking to create (data and address bus
width)? Or are you trying to create a library device?

What device and signals in the original design being used?

Derek

Presumably this depends on what ASIC libraries you have.  There is no
inherent reason that an ASIC library could not include dual-port
memories.  Apparently the original poster's didn't.

That is a clever solution that I hadn't thought of.  Of course, your
VALID_BIT array needs the capabilities of a true dual-port memory.  So
this doesn't really build a dual-port memory just out of RAMs.  It
builds it from 4 RAMs and a smaller dual-port memory (just as many
elements, but only 1 bit wide).  You would have to build that smaller
dual-port memory out of flip-flops.  The result still might be smaller
than building the full-size memory out of flip-flops.

<sharp@cadence.com> wrote in message
news:1141235829.504003.89220@z34g2000cwc.googlegroups.com...
> Presumably this depends on what ASIC libraries you have.  There is no
> inherent reason that an ASIC library could not include dual-port
> memories.  Apparently the original poster's didn't.
>

True, some TSMC ASIC libraries had dual-read/write memories, and they used
to provide
memory generators which enables creating the memory blocks of any capacity.

After we changed foundry, things got really complicated. In the new library,
only a few memories
are provided and the width & depth are also fixed. It becomes very
inefficient to use these RAMs.

I guess I am out of luck on memory issues this time.

<sharp@cadence.com> wrote in message
news:1141236232.823214.283550@j33g2000cwa.googlegroups.com...
> That is a clever solution that I hadn't thought of.  Of course, your
> VALID_BIT array needs the capabilities of a true dual-port memory.  So
> this doesn't really build a dual-port memory just out of RAMs.  It
> builds it from 4 RAMs and a smaller dual-port memory (just as many
> elements, but only 1 bit wide).  You would have to build that smaller
> dual-port memory out of flip-flops.  The result still might be smaller
> than building the full-size memory out of flip-flops.
>

Morning Samuelsson & sharp, I haven't got time to study the sequence of the
clever
solution yet. I want to know is, does it have the function of a full dual
port R/W RAM
if the R/W accesses of both ports are random? My RAM is 130*6bit, and the IP
uses
eight pieces of this RAM.

TIA

Yes, Ulf's solution gives full dual-port functionality for arbitrary
addresses (though of course you have to decide which port gets the last
word in case of simultaneous writes to the same address, as with any
dual-port memory).

But with your small word size of 6 bits, this may not be
cost-effective.  The VALID_BIT array requires similar logic to a
1-bit-wide dual-port memory (not quite the same, since port 0 always
writes a value of 0 and port 1 always writes a value of 1).  So you
have to design something close to a 130*1bit dual-port memory out of
flip-flops and logic, and use that with four 130*6bit RAMs (or two
130*6bit dual-read/single-write RAMs, since you indicated you have
those).  You might be as well off to design a 130*6bit dual-port memory
from flip-flops and logic.