DDR2 FPGA PWB SIMULATION

Greetings,
We are doing a design that uses an Altera Cyclone II to drive three DDR2
memory chips. Looking at
reference designs from Altera, TI and another company the terminations run
the spectrum from
series parallel (Altera),  just series (TI) to no resistor termination (the
other company).

So my questions are to those designers who have DDR2 interface experience
are:
 1. What kind of terminations did you use?
 2. Did you model the PWB and simulate for signal integrity?
 3. If you did sim the PWB how close did the simulation results agree with
the results from physical PWB?
 4. What simulation tool did you use, was it lumped or distributed modeling?

Regards
Jerry