Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

Hi,

Can I use Verilog or SystemVerilog to write a state machine with clock gating function?

I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine.

Thank you.

Weng

On 05/01/2019 05:29, Weng Tianxiang wrote:
> Hi,
> 
> Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
> 
> I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine.

Clock gating can be written in any language you like. It's FPGAs that 
don't support clock gating.

Nicolas

On Saturday, January 5, 2019 at 3:44:39 AM UTC-8, Nicolas Matringe wrote:
> On 05/01/2019 05:29, Weng Tianxiang wrote:
> > Hi,
> > 
> > Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
> > 
> > I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine.
> 
> Clock gating can be written in any language you like. It's FPGAs that 
> don't support clock gating.
> 
> Nicolas

Hi Nicolas,

I am asking if Verilog or SystemVerilog has the ability to automatically generate a state machine with clock gating function without any extra new statements? For example, do they have an attribute if the attribute being set the state machine generated will have the clock gating function?

At least VHDL-2008 does not have the ability.

Thank you.

Weng

On 05/01/2019 15:18, Weng Tianxiang wrote:

> Hi Nicolas,
> 
> I am asking if Verilog or SystemVerilog has the ability to automatically generate a state machine with clock gating function without any extra new statements? For example, do they have an attribute if the attribute being set the state machine generated will have the clock gating function?
> 

Well then I don't know what that "clock gating function" is, I'm sorry.

Nicolas

Apparently you cannot, but yes it can be done by others. It can also be written in VHDL but apparently you don't like how to do that so you state that it can't be done.  Perhaps you should more clearly state your problem. 

Kevin

Weng Tianxiang <wtxwtx@gmail.com> wrote:

> I am asking if Verilog or SystemVerilog has the ability to automatically
> generate a state machine with clock gating function without any extra new
> statements?

What do you mean 'extra new statements'?  This looks to me like clock
gating:


input clk;
input enable;
wire gated;

assign gated = clk & enable;

always @(posedge gated) begin
...
end


>  For example, do they have an attribute if the attribute being
> set the state machine generated will have the clock gating function?

I don't know what you mean by that.  (System)Verilog's abstraction doesn't
generate abstract state machines, it just allows you to write them. 
Whatever synthesis tools do with that code is up to them.  I presume tools
could pick up the above style if they so desire (I don't know if any ASIC
tools do but expect they would).

Theo

On 1/4/19 11:29 PM, Weng Tianxiang wrote:
> Hi,
> 
> Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
> 
> I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine.
> 
> Thank you.
> 
> Weng
> 

One big question is what do you mean by 'clock gating'

As was mentioned, one option for this is to do something like

assign gatedclk = clk & gate;

or sometimes

assign gatedclk = clk | gate;

and then us the gatedclk as the clock. The big issue with this is that
you need to worry about clock skew when you do this, as well as glitches
(the second version works better for gate changing on the rising edge of
clk, but needs to be stable before the falling edge.)

A second thing called 'clock gating' is to condition the transition on
the gate signal, something like

always @(posedge clk) begin
  if(gate) begin
... state machine here.
  end
end

This make the machine run on the original clock, but it will only change
on the cycles where the gate signal is true.

VHDL can do the same.

There is no need for a 'special statement', you just do it.  If doing
the first version, of actually gating the clock, you may want to use
some implementation defined macro function to buffer the clock and put
it into a low skew distribution network, like may have been done for the
original clock.

On Saturday, January 5, 2019 at 2:35:28 PM UTC-8, Richard Damon wrote:
> On 1/4/19 11:29 PM, Weng Tianxiang wrote:
> > Hi,
> > 
> > Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
> > 
> > I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine.
> > 
> > Thank you.
> > 
> > Weng
> > 
> 
> One big question is what do you mean by 'clock gating'
> 
> As was mentioned, one option for this is to do something like
> 
> assign gatedclk = clk & gate;
> 
> or sometimes
> 
> assign gatedclk = clk | gate;
> 
> and then us the gatedclk as the clock. The big issue with this is that
> you need to worry about clock skew when you do this, as well as glitches
> (the second version works better for gate changing on the rising edge of
> clk, but needs to be stable before the falling edge.)
> 
> A second thing called 'clock gating' is to condition the transition on
> the gate signal, something like
> 
> always @(posedge clk) begin
>   if(gate) begin
> ... state machine here.
>   end
> end
> 
> This make the machine run on the original clock, but it will only change
> on the cycles where the gate signal is true.
> 
> VHDL can do the same.
> 
> There is no need for a 'special statement', you just do it.  If doing
> the first version, of actually gating the clock, you may want to use
> some implementation defined macro function to buffer the clock and put
> it into a low skew distribution network, like may have been done for the
> original clock.

Hi Theo and Richard,

Thank you for your help.

Using clock gating function is to save power consumption. Why I ask the question is:

A cache line in Cache I, Cache II or even Cache III in a CPU usually has 64 (2**6) bytes and each cache line must have a state machine to keep data coherence among data over all situations. 

For a 6M (2**22 + 2**21) bytes cache II (the most I have seen in current market) a CPU must have at least (2**16 + 2**15) state machines, ~= 100,000, and those ~100,000 state machines don't change states most of time.

In above situation each of the ~100,000 state machines with each having more than 10 states must have a clock gating function to save power consumption: 

when it will not change states on the next cycle, a clock pulse should not be generated to keep the state unchanged and save power consumption.

Do you think if it is reasonable?

For an application implemented in a FPGA chip, the clock gating function may not be necessary because too few state machines are implemented in any normal application.

Actually I realized how to implement the power consumption scheme in VHDL as follows after the post is posted:

type STATE_TYPE is (s0, s1, ..., Sn);

signal WState, WState_NS: STATE_TYPE;

...;
a: process(clk)
begin
   if rising_edge(clk) then
      if SINI then
         WState <= S0;

      elsif WState /= WState_NS then --  WState /= WState_NS is necessary!
         WState <= WState_NS;
      end if;
   end if;
end process;

b: process(all)
begin
   case WState is
      when S0 =>
         if C00 then
            WState_NS <= S1;

         elsif C01 then
            WState_NS <= S2;

         else
            WState_NS <= S0;
         end if;

      ...;
   end case;
end process;

Thank you.

Weng

On 1/5/19 8:23 PM, Weng Tianxiang wrote:
> On Saturday, January 5, 2019 at 2:35:28 PM UTC-8, Richard Damon wrote:
>> On 1/4/19 11:29 PM, Weng Tianxiang wrote:
>>> Hi,
>>>
>>> Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
>>>
>>> I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine.
>>>
>>> Thank you.
>>>
>>> Weng
>>>
>>
>> One big question is what do you mean by 'clock gating'
>>
>> As was mentioned, one option for this is to do something like
>>
>> assign gatedclk = clk & gate;
>>
>> or sometimes
>>
>> assign gatedclk = clk | gate;
>>
>> and then us the gatedclk as the clock. The big issue with this is that
>> you need to worry about clock skew when you do this, as well as glitches
>> (the second version works better for gate changing on the rising edge of
>> clk, but needs to be stable before the falling edge.)
>>
>> A second thing called 'clock gating' is to condition the transition on
>> the gate signal, something like
>>
>> always @(posedge clk) begin
>>   if(gate) begin
>> ... state machine here.
>>   end
>> end
>>
>> This make the machine run on the original clock, but it will only change
>> on the cycles where the gate signal is true.
>>
>> VHDL can do the same.
>>
>> There is no need for a 'special statement', you just do it.  If doing
>> the first version, of actually gating the clock, you may want to use
>> some implementation defined macro function to buffer the clock and put
>> it into a low skew distribution network, like may have been done for the
>> original clock.
> 
> Hi Theo and Richard,
> 
> Thank you for your help.
> 
> Using clock gating function is to save power consumption. Why I ask the question is:
> 
> A cache line in Cache I, Cache II or even Cache III in a CPU usually has 64 (2**6) bytes and each cache line must have a state machine to keep data coherence among data over all situations. 
> 
> For a 6M (2**22 + 2**21) bytes cache II (the most I have seen in current market) a CPU must have at least (2**16 + 2**15) state machines, ~= 100,000, and those ~100,000 state machines don't change states most of time.
> 
> In above situation each of the ~100,000 state machines with each having more than 10 states must have a clock gating function to save power consumption: 
> 
> when it will not change states on the next cycle, a clock pulse should not be generated to keep the state unchanged and save power consumption.
> 
> Do you think if it is reasonable?
> 
> For an application implemented in a FPGA chip, the clock gating function may not be necessary because too few state machines are implemented in any normal application.
> > 
> Thank you.
> 
> Weng
> 

One issue with gated clocks is that each gating of the clock needs to be
considered a different clock domain from every other gating of the clock
and from the ungated clock, because the gating (and rebuffering) of the
clock introduces a delay in the clock, so you need to take precautions
when the signal passes from one domain to another. A FPGA might have,
and a gate array may provide a special circuit to generate a set of
gated clocks that will be kept in good enough alignment to not need
this, but then that would be a special application macro that needs to
be instanced.

Second, the power consumption between my first and second method (actual
gating of the clock and using a clock enable) is primarily in the power
to drive the clock line as the clock enable also keeps the state the
same in the 'skipped' clock cycle.

On Saturday, January 5, 2019 at 6:28:35 PM UTC-8, Richard Damon wrote:
> On 1/5/19 8:23 PM, Weng Tianxiang wrote:
> > On Saturday, January 5, 2019 at 2:35:28 PM UTC-8, Richard Damon wrote:
> >> On 1/4/19 11:29 PM, Weng Tianxiang wrote:
> >>> Hi,
> >>>
> >>> Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
> >>>
> >>> I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function for a state machine.
> >>>
> >>> Thank you.
> >>>
> >>> Weng
> >>>
> >>
> >> One big question is what do you mean by 'clock gating'
> >>
> >> As was mentioned, one option for this is to do something like
> >>
> >> assign gatedclk = clk & gate;
> >>
> >> or sometimes
> >>
> >> assign gatedclk = clk | gate;
> >>
> >> and then us the gatedclk as the clock. The big issue with this is that
> >> you need to worry about clock skew when you do this, as well as glitches
> >> (the second version works better for gate changing on the rising edge of
> >> clk, but needs to be stable before the falling edge.)
> >>
> >> A second thing called 'clock gating' is to condition the transition on
> >> the gate signal, something like
> >>
> >> always @(posedge clk) begin
> >>   if(gate) begin
> >> ... state machine here.
> >>   end
> >> end
> >>
> >> This make the machine run on the original clock, but it will only change
> >> on the cycles where the gate signal is true.
> >>
> >> VHDL can do the same.
> >>
> >> There is no need for a 'special statement', you just do it.  If doing
> >> the first version, of actually gating the clock, you may want to use
> >> some implementation defined macro function to buffer the clock and put
> >> it into a low skew distribution network, like may have been done for the
> >> original clock.
> > 
> > Hi Theo and Richard,
> > 
> > Thank you for your help.
> > 
> > Using clock gating function is to save power consumption. Why I ask the question is:
> > 
> > A cache line in Cache I, Cache II or even Cache III in a CPU usually has 64 (2**6) bytes and each cache line must have a state machine to keep data coherence among data over all situations. 
> > 
> > For a 6M (2**22 + 2**21) bytes cache II (the most I have seen in current market) a CPU must have at least (2**16 + 2**15) state machines, ~= 100,000, and those ~100,000 state machines don't change states most of time.
> > 
> > In above situation each of the ~100,000 state machines with each having more than 10 states must have a clock gating function to save power consumption: 
> > 
> > when it will not change states on the next cycle, a clock pulse should not be generated to keep the state unchanged and save power consumption.
> > 
> > Do you think if it is reasonable?
> > 
> > For an application implemented in a FPGA chip, the clock gating function may not be necessary because too few state machines are implemented in any normal application.
> > > 
> > Thank you.
> > 
> > Weng
> > 
> 
> One issue with gated clocks is that each gating of the clock needs to be
> considered a different clock domain from every other gating of the clock
> and from the ungated clock, because the gating (and rebuffering) of the
> clock introduces a delay in the clock, so you need to take precautions
> when the signal passes from one domain to another. A FPGA might have,
> and a gate array may provide a special circuit to generate a set of
> gated clocks that will be kept in good enough alignment to not need
> this, but then that would be a special application macro that needs to
> be instanced.
> 
> Second, the power consumption between my first and second method (actual
> gating of the clock and using a clock enable) is primarily in the power
> to drive the clock line as the clock enable also keeps the state the
> same in the 'skipped' clock cycle.

Hi Richard,

There are 2 things to consider on how to generate a clock gating function:
1. Generate CE logic.
2. Make gated clock signal working properly.

You address the part 2) and I emphasize on the part 1). 

Is it complex to generate CE logic?

In my understanding generating a clock pulse is consuming more power than skipping the clock pulse.

I want to know if each of CPU ~100,000 state machine implementation actually has clock gating function. 

Based on your code I think it is reasonable to think each of CPU ~100,000 state machine implementation actually has clock gating function.

Only CPU designers know their implementation. I need the information.

Thank you.

Weng