Altera Cyclone replacement

On Monday, January 28, 2019 at 3:55:24 AM UTC-5, Stef wrote:
> On 2019-01-25 Adam Górski wrote in comp.arch.fpga:
> > On 2019-01-25 15:58, Stef wrote:
> >> Hi,
> >> 
> >> We got an old design with an Altera Cyclone FPGA (EP1C12F324).
> >> These are probably obsolete (Can't find any info on them on the Intel
> >> site, Farnell is out of stock, etc.). Currently active are the Cyclone-IV
> >> and Cyclone-V if I understood correctly.
> >> 
> >> Is a design from a Cyclone portable to a Cyclone-IV/V? What kind of
> >> changes should I expect to code and board? Design includes NIOS.
> >> 
> >> Or alternatively, are their sources for these old Cyclone chips?
> >> (We actually would need 3 different types :-( )
> >> 
> >> 
> >
> > Hi,
> >
> > Are you looking for somebody who can transfer you project from Altera 
> > Cyclone to Cyclone V ?
> 
> Not for now, but who knows. Will be to Cyclone 10 or Max 10 then after
> recent discoveries. ;-)

If you are porting to a new family, why limit yourself to Cyclones?  If the HDL was written without using specific device features, you can likely port it as easily to another brand as to a new device.  Xilinx and Lattice and even Microsemi make competitive FPGAs.  But then I suppose there is a license issue with using NIOS on something other than an Altera part.  That's another reason why I don't use proprietary code in my designs.  

At one time I worked for a company who used a lot of FPGAs.  They didn't have brand loyalty.  They would use whichever device was best for a given design.  So their policy was to not use anything specific to a brand... well, for the most part.  I recall we got a demonstration one day by my boss who had created a design which needed to be updated.  Seems he had included one tiny piece that required hand routing in the chip editor to meet the timing spec... and had not documented this anywhere!!!  So we received a bit of oral tradition.  This company makes test equipment that is sold to all the major comms manufacturers.  lol!  

Given that Altera is now owned by Intel, I would use this opportunity to replace the NIOS processor with something independent of device manufacturer and remove your brand dependency.  There are tons of third party processors out there.  I can recommend one if you need. 


  Rick C.

  + Get 6 months of free supercharging
  + Tesla referral code - https://ts.la/richard11209

On Monday, January 28, 2019 at 6:28:05 AM UTC-5, gnuarm.del...@gmail.com wrote:
> On Monday, January 28, 2019 at 3:55:24 AM UTC-5, Stef wrote:
> > On 2019-01-25 Adam Górski wrote in comp.arch.fpga:
> > > On 2019-01-25 15:58, Stef wrote:
> > >> Hi,
> > >> 
> > >> We got an old design with an Altera Cyclone FPGA (EP1C12F324).
> > >> These are probably obsolete (Can't find any info on them on the Intel
> > >> site, Farnell is out of stock, etc.). Currently active are the Cyclone-IV
> > >> and Cyclone-V if I understood correctly.
> > >> 
> > >> Is a design from a Cyclone portable to a Cyclone-IV/V? What kind of
> > >> changes should I expect to code and board? Design includes NIOS.
> > >> 
> > >> Or alternatively, are their sources for these old Cyclone chips?
> > >> (We actually would need 3 different types :-( )
> > >> 
> > >> 
> > >
> > > Hi,
> > >
> > > Are you looking for somebody who can transfer you project from Altera 
> > > Cyclone to Cyclone V ?
> > 
> > Not for now, but who knows. Will be to Cyclone 10 or Max 10 then after
> > recent discoveries. ;-)
> 
> If you are porting to a new family, why limit yourself to Cyclones?  If the HDL was written without using specific device features, you can likely port it as easily to another brand as to a new device.  Xilinx and Lattice and even Microsemi make competitive FPGAs.  But then I suppose there is a license issue with using NIOS on something other than an Altera part.  That's another reason why I don't use proprietary code in my designs.  
> 
> At one time I worked for a company who used a lot of FPGAs.  They didn't have brand loyalty.  They would use whichever device was best for a given design.  So their policy was to not use anything specific to a brand... well, for the most part.  I recall we got a demonstration one day by my boss who had created a design which needed to be updated.  Seems he had included one tiny piece that required hand routing in the chip editor to meet the timing spec... and had not documented this anywhere!!!  So we received a bit of oral tradition.  This company makes test equipment that is sold to all the major comms manufacturers.  lol!  
> 
> Given that Altera is now owned by Intel, I would use this opportunity to replace the NIOS processor with something independent of device manufacturer and remove your brand dependency.  There are tons of third party processors out there.  I can recommend one if you need. 
> 
> 
>   Rick C.
> 
>   + Get 6 months of free supercharging
>   + Tesla referral code - https://ts.la/richard11209


This is an excellent point!  The company I work for is a design partner for both Brand A/I and Brand X so I'm hesitant speak poorly of either.  However, after the acquisition in 2016, it appears that Intel halted *everything* in the Altera business and they're still catching up with the rebranding on all of their documentation, website, etc.  Their forums are still a real mess, so even searching for solutions is a challenge.  

For anyone in the same position as the OP, if the sales volumes and the forecast are long enough, I'd recommend retargeting another device, preferably Xilinx.  If your projected volume is high enough that you aren't going to be able to find drop-in parts on the market, you're going to be looking at a board respin for the new devices (or an interposer, if possible) and some porting effort anyway.  You may as well take the opportunity to "future proof" the design by migrating to another vendor that isn't likely to get acquired or axed.  Xilinx has the single core Zynq-7000 devices if you want to go with a more main-stream, ARM processor sub-system (although likely overkill for whatever your Nios is doing).  Otherwise, the Artix-7 and Spartan-7 would be good targets if you want to migrate to a Microblaze or some other soft core.  The Spartan-7 family is essentially the Artix-7 fabric with the transcievers removed and are offered in 6K to 100K logic cell densities.

On Monday, January 28, 2019 at 10:49:32 AM UTC-5, kkoorndyk wrote:
You may as well take the opportunity to "future proof" the design by migrating to another vendor that isn't likely to get acquired or axed.  Xilinx has the single core Zynq-7000 devices if you want to go with a more main-stream, ARM processor sub-system (although likely overkill for whatever your Nios is doing).  Otherwise, the Artix-7 and Spartan-7 would be good targets if you want to migrate to a Microblaze or some other soft core.  The Spartan-7 family is essentially the Artix-7 fabric with the transcievers removed and are offered in 6K to 100K logic cell densities.

I don't think you actually got my point.  Moving to a Spartan by using a MicroBlaze processor isn't "future proofing" anything.  It is just shifting from one brand to another with the exact same problems.  

If you want to future proof a soft CPU design you need to drop any FPGA company in-house processor and use an open source processor design.  Then you can use any FPGA you wish.  

Here is some info on the J1, an open source processor that was used to replace a microblaze when it became unequal to the task at hand.  

http://www.forth.org/svfig/kk/11-2010-Bowman.pdf

http://www.excamera.com/sphinx/fpga-j1.html

http://www.excamera.com/files/j1.pdf


  Rick C.

  -- Get 6 months of free supercharging
  -- Tesla referral code - https://ts.la/richard11209

On 2019-01-28 gnuarm.deletethisbit@gmail.com wrote in comp.arch.fpga:
> On Monday, January 28, 2019 at 3:55:24 AM UTC-5, Stef wrote:
>> 
>> Not for now, but who knows. Will be to Cyclone 10 or Max 10 then after
>> recent discoveries. ;-)
>
> If you are porting to a new family, why limit yourself to Cyclones?  If the HDL was written without using specific device features, you can likely port it as easily to another brand as to a new device.  Xilinx and Lattice and even Microsemi make competitive FPGAs.  But then I suppose there is a license issue with using NIOS on something other than an Altera part.  That's another reason why I don't use proprietary code in my designs.  

I was under the assumption that porting to Cyclones would be less work than
moving to other families/manufacturers. And I think that is still the case
if NIOS is part of the existing design.

If it really comes to porting to another architecture, we might even port
the whole thing to a microcontroller. As far as we can see now, there was
no real need for an FPGA in that design. I/O might be a problem, but that
is one of the thing to investigate if it comes to porting.

-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Pohl's law:
         Nothing is so good that somebody, somewhere, will not hate it.

On Wednesday, January 30, 2019 at 3:44:08 AM UTC-5, Stef wrote:
> On 2019-01-28 gnuarm.deletethisbit@gmail.com wrote in comp.arch.fpga:
> > On Monday, January 28, 2019 at 3:55:24 AM UTC-5, Stef wrote:
> >> 
> >> Not for now, but who knows. Will be to Cyclone 10 or Max 10 then after
> >> recent discoveries. ;-)
> >
> > If you are porting to a new family, why limit yourself to Cyclones?  If the HDL was written without using specific device features, you can likely port it as easily to another brand as to a new device.  Xilinx and Lattice and even Microsemi make competitive FPGAs.  But then I suppose there is a license issue with using NIOS on something other than an Altera part.  That's another reason why I don't use proprietary code in my designs.  
> 
> I was under the assumption that porting to Cyclones would be less work than
> moving to other families/manufacturers. And I think that is still the case
> if NIOS is part of the existing design.
> 
> If it really comes to porting to another architecture, we might even port
> the whole thing to a microcontroller. As far as we can see now, there was
> no real need for an FPGA in that design. I/O might be a problem, but that
> is one of the thing to investigate if it comes to porting.

Don't suggest to me that an FPGA design should be ported to an MCU.  I'm in the other camp that MCU designs can often be effectively ported to FPGAs.  I find the issues with sharing a single CPU to perform multiple tasks in real time to be much greater than the issues of fitting a design into an FPGA.  People cite all sorts of "facts" about using FPGAs that don't seem to apply in my designs, so I'm not sure what they are doing wrong.  I find FPGAs to be easy to design and work with.  I also find much fewer problems on the lab bench and in the field than others do with software based designs.  

But certainly the easy route is to continue making the boards with the old parts.  Just be careful of your sources and verify each lot of devices you buy before using them in a design.  There are a lot of counterfeits these days.  EOL devices are popular targets. 


  Rick C.

  -+ Get 6 months of free supercharging
  -+ Tesla referral code - https://ts.la/richard11209

On Tuesday, January 29, 2019 at 7:57:05 PM UTC-5, gnuarm.del...@gmail.com wrote:
> On Monday, January 28, 2019 at 10:49:32 AM UTC-5, kkoorndyk wrote:
> You may as well take the opportunity to "future proof" the design by migrating to another vendor that isn't likely to get acquired or axed.  Xilinx has the single core Zynq-7000 devices if you want to go with a more main-stream, ARM processor sub-system (although likely overkill for whatever your Nios is doing).  Otherwise, the Artix-7 and Spartan-7 would be good targets if you want to migrate to a Microblaze or some other soft core.  The Spartan-7 family is essentially the Artix-7 fabric with the transcievers removed and are offered in 6K to 100K logic cell densities.
> 
> I don't think you actually got my point.  Moving to a Spartan by using a MicroBlaze processor isn't "future proofing" anything.  It is just shifting from one brand to another with the exact same problems.  
> 
> If you want to future proof a soft CPU design you need to drop any FPGA company in-house processor and use an open source processor design.  Then you can use any FPGA you wish.  
> 
> Here is some info on the J1, an open source processor that was used to replace a microblaze when it became unequal to the task at hand.  
> 
> http://www.forth.org/svfig/kk/11-2010-Bowman.pdf
> 
> http://www.excamera.com/sphinx/fpga-j1.html
> 
> http://www.excamera.com/files/j1.pdf
> 
> 
>   Rick C.
> 
>   -- Get 6 months of free supercharging
>   -- Tesla referral code - https://ts.la/richard11209

No, I got your point perfectly, hence the following part of my recommendation:  "or some other soft core."

If the original Nios was employed, I'm not entirely convinced a soft core is necessary (yet).  How simple is the software running on it?  Can it reasonably be ported to HDL, thus ensuring portability?  I tend to lean that way unless the SW was simple due to capability limitations in the earlier technologies (e.g., old Cyclone and Nios) and the desire is to add more features that are realizable with new generation devices and soft (or hard) core capabilities.

On Wednesday, January 30, 2019 at 11:24:17 AM UTC-5, kkoorndyk wrote:
> On Tuesday, January 29, 2019 at 7:57:05 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > On Monday, January 28, 2019 at 10:49:32 AM UTC-5, kkoorndyk wrote:
> > You may as well take the opportunity to "future proof" the design by migrating to another vendor that isn't likely to get acquired or axed.  Xilinx has the single core Zynq-7000 devices if you want to go with a more main-stream, ARM processor sub-system (although likely overkill for whatever your Nios is doing).  Otherwise, the Artix-7 and Spartan-7 would be good targets if you want to migrate to a Microblaze or some other soft core.  The Spartan-7 family is essentially the Artix-7 fabric with the transcievers removed and are offered in 6K to 100K logic cell densities.
> > 
> > I don't think you actually got my point.  Moving to a Spartan by using a MicroBlaze processor isn't "future proofing" anything.  It is just shifting from one brand to another with the exact same problems.  
> > 
> > If you want to future proof a soft CPU design you need to drop any FPGA company in-house processor and use an open source processor design.  Then you can use any FPGA you wish.  
> > 
> > Here is some info on the J1, an open source processor that was used to replace a microblaze when it became unequal to the task at hand.  
> > 
> > http://www.forth.org/svfig/kk/11-2010-Bowman.pdf
> > 
> > http://www.excamera.com/sphinx/fpga-j1.html
> > 
> > http://www.excamera.com/files/j1.pdf
> > 
> > 
> >   Rick C.
> > 
> >   -- Get 6 months of free supercharging
> >   -- Tesla referral code - https://ts.la/richard11209
> 
> No, I got your point perfectly, hence the following part of my recommendation:  "or some other soft core."

I am making the point that porting from one proprietary processor to another is of limited value.  Microblaze is proprietary.  I believe there may be some open source versions available, but I expect there are open source versions of the NIOS available as well.  But perhaps more importantly, they are far from optimal.  That's why I posted the info on the J1 processor.  It was invented to replace a Microblaze that wasn't up to the task.  


> If the original Nios was employed, I'm not entirely convinced a soft core is necessary (yet).  How simple is the software running on it?  Can it reasonably be ported to HDL, thus ensuring portability?  I tend to lean that way unless the SW was simple due to capability limitations in the earlier technologies (e.g., old Cyclone and Nios) and the desire is to add more features that are realizable with new generation devices and soft (or hard) core capabilities.

Sometimes soft CPUs are added to reduce the size of logic.  Other times they are added because of the complexity of expression.  Regardless of how simply we can write HDL, the large part of the engineering world perceives HDL as much more complex than other languages and are not willing to port code to an HDL unless absolutely required.  So if the code is currently in C, it won't get ported to HDL without a compelling reason. 

Personally I think Xilinx and Altera are responsible for the present perception that FPGAs are difficult to use, expensive, large and power hungry.  That is largely true if you use their products only.  Lattice has been addressing a newer market with small, low power, inexpensive devices intended for the mobile market.  Now if someone would approach the issue of ease of use by something more than throwing an IDE on top of their command line tools, the FPGA market can explode into territory presently dominated by MCUs.  

Does anyone really think toasters can only be controlled by MCUs?  We just need a cheap enough FPGA in a suitable package.  


  Rick C.

  +- Get 6 months of free supercharging
  +- Tesla referral code - https://ts.la/richard11209

On Wednesday, January 30, 2019 at 11:14:26 AM UTC-6, gnuarm.del...@gmail.co=
m wrote:
> On Wednesday, January 30, 2019 at 11:24:17 AM UTC-5, kkoorndyk wrote:
> > On Tuesday, January 29, 2019 at 7:57:05 PM UTC-5, gnuarm.del...@gmail.c=
om wrote:
> > > On Monday, January 28, 2019 at 10:49:32 AM UTC-5, kkoorndyk wrote:
> > > You may as well take the opportunity to "future proof" the design by =
migrating to another vendor that isn't likely to get acquired or axed.  Xil=
inx has the single core Zynq-7000 devices if you want to go with a more mai=
n-stream, ARM processor sub-system (although likely overkill for whatever y=
our Nios is doing).  Otherwise, the Artix-7 and Spartan-7 would be good tar=
gets if you want to migrate to a Microblaze or some other soft core.  The S=
partan-7 family is essentially the Artix-7 fabric with the transcievers rem=
oved and are offered in 6K to 100K logic cell densities.
> > >=20
> > > I don't think you actually got my point.  Moving to a Spartan by usin=
g a MicroBlaze processor isn't "future proofing" anything.  It is just shif=
ting from one brand to another with the exact same problems. =20
> > >=20
> > > If you want to future proof a soft CPU design you need to drop any FP=
GA company in-house processor and use an open source processor design.  The=
n you can use any FPGA you wish. =20
> > >=20
> > > Here is some info on the J1, an open source processor that was used t=
o replace a microblaze when it became unequal to the task at hand. =20
> > >=20
> > > http://www.forth.org/svfig/kk/11-2010-Bowman.pdf
> > >=20
> > > http://www.excamera.com/sphinx/fpga-j1.html
> > >=20
> > > http://www.excamera.com/files/j1.pdf
> > >=20
> > >=20
> > >   Rick C.
> > >=20
> > >   -- Get 6 months of free supercharging
> > >   -- Tesla referral code - https://ts.la/richard11209
> >=20
> > No, I got your point perfectly, hence the following part of my recommen=
dation:  "or some other soft core."
>=20
> I am making the point that porting from one proprietary processor to anot=
her is of limited value.  Microblaze is proprietary.  I believe there may b=
e some open source versions available, but I expect there are open source v=
ersions of the NIOS available as well.  But perhaps more importantly, they =
are far from optimal.  That's why I posted the info on the J1 processor.  I=
t was invented to replace a Microblaze that wasn't up to the task. =20
>=20
>=20
> > If the original Nios was employed, I'm not entirely convinced a soft co=
re is necessary (yet).  How simple is the software running on it?  Can it r=
easonably be ported to HDL, thus ensuring portability?  I tend to lean that=
 way unless the SW was simple due to capability limitations in the earlier =
technologies (e.g., old Cyclone and Nios) and the desire is to add more fea=
tures that are realizable with new generation devices and soft (or hard) co=
re capabilities.
>=20
> Sometimes soft CPUs are added to reduce the size of logic.  Other times t=
hey are added because of the complexity of expression.  Regardless of how s=
imply we can write HDL, the large part of the engineering world perceives H=
DL as much more complex than other languages and are not willing to port co=
de to an HDL unless absolutely required.  So if the code is currently in C,=
 it won't get ported to HDL without a compelling reason.=20
>=20
> Personally I think Xilinx and Altera are responsible for the present perc=
eption that FPGAs are difficult to use, expensive, large and power hungry. =
 That is largely true if you use their products only.  Lattice has been add=
ressing a newer market with small, low power, inexpensive devices intended =
for the mobile market.  Now if someone would approach the issue of ease of =
use by something more than throwing an IDE on top of their command line too=
ls, the FPGA market can explode into territory presently dominated by MCUs.=
 =20
>=20
> Does anyone really think toasters can only be controlled by MCUs?  We jus=
t need a cheap enough FPGA in a suitable package. =20
>=20
>=20
>   Rick C.
>=20
>   +- Get 6 months of free supercharging
>   +- Tesla referral code - https://ts.la/richard11209

]>Microblaze is proprietary.  I believe there may be some open source versi=
ons available, but I expect there are open source versions of the NIOS avai=
lable as well.

Microblaze clones: aeMB, an-noc-mpsoc, mblite, mb-lite-plus, myblaze, openf=
ire_core, openfire2, secretblaze

No NIOS clones that I know of

]>But perhaps more importantly, they are far from optimal.
Ugh, they have some of the best figure-of-merit numbers available.
  (Instructions per second per LUT)
And are available in many configuration options.

There are a large variety of RISC-V cores available some of which have low =
LUT counts.

Jim Brakefield

On Wednesday, January 30, 2019 at 7:42:54 PM UTC-5, jim.bra...@ieee.org wro=
te:
> On Wednesday, January 30, 2019 at 11:14:26 AM UTC-6, gnuarm.del...@gmail.=
com wrote:
> > On Wednesday, January 30, 2019 at 11:24:17 AM UTC-5, kkoorndyk wrote:
> > > On Tuesday, January 29, 2019 at 7:57:05 PM UTC-5, gnuarm.del...@gmail=
.com wrote:
> > > > On Monday, January 28, 2019 at 10:49:32 AM UTC-5, kkoorndyk wrote:
> > > > You may as well take the opportunity to "future proof" the design b=
y migrating to another vendor that isn't likely to get acquired or axed.  X=
ilinx has the single core Zynq-7000 devices if you want to go with a more m=
ain-stream, ARM processor sub-system (although likely overkill for whatever=
 your Nios is doing).  Otherwise, the Artix-7 and Spartan-7 would be good t=
argets if you want to migrate to a Microblaze or some other soft core.  The=
 Spartan-7 family is essentially the Artix-7 fabric with the transcievers r=
emoved and are offered in 6K to 100K logic cell densities.
> > > >=20
> > > > I don't think you actually got my point.  Moving to a Spartan by us=
ing a MicroBlaze processor isn't "future proofing" anything.  It is just sh=
ifting from one brand to another with the exact same problems. =20
> > > >=20
> > > > If you want to future proof a soft CPU design you need to drop any =
FPGA company in-house processor and use an open source processor design.  T=
hen you can use any FPGA you wish. =20
> > > >=20
> > > > Here is some info on the J1, an open source processor that was used=
 to replace a microblaze when it became unequal to the task at hand. =20
> > > >=20
> > > > http://www.forth.org/svfig/kk/11-2010-Bowman.pdf
> > > >=20
> > > > http://www.excamera.com/sphinx/fpga-j1.html
> > > >=20
> > > > http://www.excamera.com/files/j1.pdf
> > > >=20
> > > >=20
> > > >   Rick C.
> > > >=20
> > > >   -- Get 6 months of free supercharging
> > > >   -- Tesla referral code - https://ts.la/richard11209
> > >=20
> > > No, I got your point perfectly, hence the following part of my recomm=
endation:  "or some other soft core."
> >=20
> > I am making the point that porting from one proprietary processor to an=
other is of limited value.  Microblaze is proprietary.  I believe there may=
 be some open source versions available, but I expect there are open source=
 versions of the NIOS available as well.  But perhaps more importantly, the=
y are far from optimal.  That's why I posted the info on the J1 processor. =
 It was invented to replace a Microblaze that wasn't up to the task. =20
> >=20
> >=20
> > > If the original Nios was employed, I'm not entirely convinced a soft =
core is necessary (yet).  How simple is the software running on it?  Can it=
 reasonably be ported to HDL, thus ensuring portability?  I tend to lean th=
at way unless the SW was simple due to capability limitations in the earlie=
r technologies (e.g., old Cyclone and Nios) and the desire is to add more f=
eatures that are realizable with new generation devices and soft (or hard) =
core capabilities.
> >=20
> > Sometimes soft CPUs are added to reduce the size of logic.  Other times=
 they are added because of the complexity of expression.  Regardless of how=
 simply we can write HDL, the large part of the engineering world perceives=
 HDL as much more complex than other languages and are not willing to port =
code to an HDL unless absolutely required.  So if the code is currently in =
C, it won't get ported to HDL without a compelling reason.=20
> >=20
> > Personally I think Xilinx and Altera are responsible for the present pe=
rception that FPGAs are difficult to use, expensive, large and power hungry=
.  That is largely true if you use their products only.  Lattice has been a=
ddressing a newer market with small, low power, inexpensive devices intende=
d for the mobile market.  Now if someone would approach the issue of ease o=
f use by something more than throwing an IDE on top of their command line t=
ools, the FPGA market can explode into territory presently dominated by MCU=
s. =20
> >=20
> > Does anyone really think toasters can only be controlled by MCUs?  We j=
ust need a cheap enough FPGA in a suitable package. =20
> >=20
> >=20
> >   Rick C.
> >=20
> >   +- Get 6 months of free supercharging
> >   +- Tesla referral code - https://ts.la/richard11209
>=20
> ]>Microblaze is proprietary.  I believe there may be some open source ver=
sions available, but I expect there are open source versions of the NIOS av=
ailable as well.
>=20
> Microblaze clones: aeMB, an-noc-mpsoc, mblite, mb-lite-plus, myblaze, ope=
nfire_core, openfire2, secretblaze
>=20
> No NIOS clones that I know of
>=20
> ]>But perhaps more importantly, they are far from optimal.
> Ugh, they have some of the best figure-of-merit numbers available.
>   (Instructions per second per LUT)
> And are available in many configuration options.
>=20
> There are a large variety of RISC-V cores available some of which have lo=
w LUT counts.
>=20
> Jim Brakefield

Not sure what figures you are talking about.  Has anyone compiled a compari=
son? =20


  Rick C.

  ++ Get 6 months of free supercharging
  ++ Tesla referral code - https://ts.la/richard11209

On Wednesday, January 30, 2019 at 7:37:56 PM UTC-6, gnuarm.del...@gmail.com=
 wrote:
> On Wednesday, January 30, 2019 at 7:42:54 PM UTC-5, jim.bra...@ieee.org w=
rote:
> > On Wednesday, January 30, 2019 at 11:14:26 AM UTC-6, gnuarm.del...@gmai=
l.com wrote:
> > > On Wednesday, January 30, 2019 at 11:24:17 AM UTC-5, kkoorndyk wrote:
> > > > On Tuesday, January 29, 2019 at 7:57:05 PM UTC-5, gnuarm.del...@gma=
il.com wrote:
> > > > > On Monday, January 28, 2019 at 10:49:32 AM UTC-5, kkoorndyk wrote=
:
> > > > > You may as well take the opportunity to "future proof" the design=
 by migrating to another vendor that isn't likely to get acquired or axed. =
 Xilinx has the single core Zynq-7000 devices if you want to go with a more=
 main-stream, ARM processor sub-system (although likely overkill for whatev=
er your Nios is doing).  Otherwise, the Artix-7 and Spartan-7 would be good=
 targets if you want to migrate to a Microblaze or some other soft core.  T=
he Spartan-7 family is essentially the Artix-7 fabric with the transcievers=
 removed and are offered in 6K to 100K logic cell densities.
> > > > >=20
> > > > > I don't think you actually got my point.  Moving to a Spartan by =
using a MicroBlaze processor isn't "future proofing" anything.  It is just =
shifting from one brand to another with the exact same problems. =20
> > > > >=20
> > > > > If you want to future proof a soft CPU design you need to drop an=
y FPGA company in-house processor and use an open source processor design. =
 Then you can use any FPGA you wish. =20
> > > > >=20
> > > > > Here is some info on the J1, an open source processor that was us=
ed to replace a microblaze when it became unequal to the task at hand. =20
> > > > >=20
> > > > > http://www.forth.org/svfig/kk/11-2010-Bowman.pdf
> > > > >=20
> > > > > http://www.excamera.com/sphinx/fpga-j1.html
> > > > >=20
> > > > > http://www.excamera.com/files/j1.pdf
> > > > >=20
> > > > >=20
> > > > >   Rick C.
> > > > >=20
> > > > >   -- Get 6 months of free supercharging
> > > > >   -- Tesla referral code - https://ts.la/richard11209
> > > >=20
> > > > No, I got your point perfectly, hence the following part of my reco=
mmendation:  "or some other soft core."
> > >=20
> > > I am making the point that porting from one proprietary processor to =
another is of limited value.  Microblaze is proprietary.  I believe there m=
ay be some open source versions available, but I expect there are open sour=
ce versions of the NIOS available as well.  But perhaps more importantly, t=
hey are far from optimal.  That's why I posted the info on the J1 processor=
.  It was invented to replace a Microblaze that wasn't up to the task. =20
> > >=20
> > >=20
> > > > If the original Nios was employed, I'm not entirely convinced a sof=
t core is necessary (yet).  How simple is the software running on it?  Can =
it reasonably be ported to HDL, thus ensuring portability?  I tend to lean =
that way unless the SW was simple due to capability limitations in the earl=
ier technologies (e.g., old Cyclone and Nios) and the desire is to add more=
 features that are realizable with new generation devices and soft (or hard=
) core capabilities.
> > >=20
> > > Sometimes soft CPUs are added to reduce the size of logic.  Other tim=
es they are added because of the complexity of expression.  Regardless of h=
ow simply we can write HDL, the large part of the engineering world perceiv=
es HDL as much more complex than other languages and are not willing to por=
t code to an HDL unless absolutely required.  So if the code is currently i=
n C, it won't get ported to HDL without a compelling reason.=20
> > >=20
> > > Personally I think Xilinx and Altera are responsible for the present =
perception that FPGAs are difficult to use, expensive, large and power hung=
ry.  That is largely true if you use their products only.  Lattice has been=
 addressing a newer market with small, low power, inexpensive devices inten=
ded for the mobile market.  Now if someone would approach the issue of ease=
 of use by something more than throwing an IDE on top of their command line=
 tools, the FPGA market can explode into territory presently dominated by M=
CUs. =20
> > >=20
> > > Does anyone really think toasters can only be controlled by MCUs?  We=
 just need a cheap enough FPGA in a suitable package. =20
> > >=20
> > >=20
> > >   Rick C.
> > >=20
> > >   +- Get 6 months of free supercharging
> > >   +- Tesla referral code - https://ts.la/richard11209
> >=20
> > ]>Microblaze is proprietary.  I believe there may be some open source v=
ersions available, but I expect there are open source versions of the NIOS =
available as well.
> >=20
> > Microblaze clones: aeMB, an-noc-mpsoc, mblite, mb-lite-plus, myblaze, o=
penfire_core, openfire2, secretblaze
> >=20
> > No NIOS clones that I know of
> >=20
> > ]>But perhaps more importantly, they are far from optimal.
> > Ugh, they have some of the best figure-of-merit numbers available.
> >   (Instructions per second per LUT)
> > And are available in many configuration options.
> >=20
> > There are a large variety of RISC-V cores available some of which have =
low LUT counts.
> >=20
> > Jim Brakefield
>=20
> Not sure what figures you are talking about.  Has anyone compiled a compa=
rison? =20
>=20
>=20
>   Rick C.
>=20
>   ++ Get 6 months of free supercharging
>   ++ Tesla referral code - https://ts.la/richard11209

Altera/Intel: "Nios II Performance Benchmarks
Xilinx: appendix of MicroBlaze Processor Reference Guide