Tiny CPUs for Slow Logic

Most of us have implemented small processors for logic operations that don't need to happen at high speed.  Simple CPUs can be built into an FPGA using a very small footprint much like the ALU blocks.  There are stack based processors that are very small, smaller than even a few kB of memory.  

If they were easily programmable in something other than C would anyone be interested?  Or is a C compiler mandatory even for processors running very small programs?  

I am picturing this not terribly unlike the sequencer I used many years ago on an I/O board for an array processor which had it's own assembler.  It was very simple and easy to use, but very much not a high level language.  This would have a language that was high level, just not C rather something extensible and simple to use and potentially interactive. 

Rick C.

On 19/03/2019 01:13, gnuarm.deletethisbit@gmail.com wrote:
> Most of us have implemented small processors for logic operations
> that don't need to happen at high speed.  Simple CPUs can be built
> into an FPGA using a very small footprint much like the ALU blocks.
> There are stack based processors that are very small, smaller than
> even a few kB of memory.
> 
> If they were easily programmable in something other than C would
> anyone be interested?  Or is a C compiler mandatory even for
> processors running very small programs?
> 
> I am picturing this not terribly unlike the sequencer I used many
> years ago on an I/O board for an array processor which had it's own
> assembler.  It was very simple and easy to use, but very much not a
> high level language.  This would have a language that was high level,
> just not C rather something extensible and simple to use and
> potentially interactive.
> 
> Rick C.
> 

If it is going to appeal to software developers, you need C.  And it has
to be reasonable, standard C, even if it is for small devices -
programmers are fed up with the pains needed for special device-specific
C on 8051, AVR, PIC, etc.  That does not necessarily mean it has to be
fast, but it should work with standard language.  Having 16-bit size
rather than 8-bit size makes a huge difference to how programmers feel
about the device - aim for something like the msp430.

You might, however, want to look at extensions for CSP-style
communication between cpus - something like XMOS XC.

If it is to appeal to hardware (FPGA) developers, C might not be as
essential.  Some other kind of high level language, perhaps centred
around state machines, might work.

But when I see "extensible, simple to use and potentially interactive",
I fear someone is thinking of Forth.  People who are very used to Forth
find it a great language - but you need to understand that /nobody/
wants to learn it.  Most programmers would rather work in assembler than
Forth.  You can argue that this attitude is irrational, and that Forth
is not harder than other languages - you might be right.  But that
doesn't change matters.

On Tuesday, March 19, 2019 at 4:15:47 AM UTC-4, David Brown wrote:
> On 19/03/2019 01:13, gnuarm.deletethisbit@gmail.com wrote:
> > Most of us have implemented small processors for logic operations
> > that don't need to happen at high speed.  Simple CPUs can be built
> > into an FPGA using a very small footprint much like the ALU blocks.
> > There are stack based processors that are very small, smaller than
> > even a few kB of memory.
> > 
> > If they were easily programmable in something other than C would
> > anyone be interested?  Or is a C compiler mandatory even for
> > processors running very small programs?
> > 
> > I am picturing this not terribly unlike the sequencer I used many
> > years ago on an I/O board for an array processor which had it's own
> > assembler.  It was very simple and easy to use, but very much not a
> > high level language.  This would have a language that was high level,
> > just not C rather something extensible and simple to use and
> > potentially interactive.
> > 
> > Rick C.
> > 
> 
> If it is going to appeal to software developers, you need C.  And it has
> to be reasonable, standard C, even if it is for small devices -
> programmers are fed up with the pains needed for special device-specific
> C on 8051, AVR, PIC, etc.  That does not necessarily mean it has to be
> fast, but it should work with standard language.  Having 16-bit size
> rather than 8-bit size makes a huge difference to how programmers feel
> about the device - aim for something like the msp430.
> 
> You might, however, want to look at extensions for CSP-style
> communication between cpus - something like XMOS XC.
> 
> If it is to appeal to hardware (FPGA) developers, C might not be as
> essential.  Some other kind of high level language, perhaps centred
> around state machines, might work.
> 
> But when I see "extensible, simple to use and potentially interactive",
> I fear someone is thinking of Forth.  People who are very used to Forth
> find it a great language - but you need to understand that /nobody/
> wants to learn it.  Most programmers would rather work in assembler than
> Forth.  You can argue that this attitude is irrational, and that Forth
> is not harder than other languages - you might be right.  But that
> doesn't change matters.

Certainly this would be like Forth, but the reality is I'm thinking of a Forth like CPU because they can be designed so simply.  

The F18A stack processor designed by Charles Moore is used in the GA144 chip.  There are 144 of them with unusual interconnections that allow the CPU to halt waiting for communications, saving power.  The CPU is so small that it could be included in an FPGA as what would be equivalent to a logic element.  

In the same way that the other functional logic elements like the block RAMs and DSP blocks are used for custom functionality which requires the designer to program by whatever means is devised, these tiny CPUs would not need a high level language like C.  The code in them would be small enough to be considered "logic" and developed at the assembly level. 

People have mindsets about things and I believe this is one of them.  The GA144 is not so easy to program because people want to use it for the sort of large programs they write for other fast CPUs.  In an FPGA a very fast processor can be part of the logic rather than an uber-controller riding herd over the whole chip.  But this would require designers to change their thinking of how to use CPUs.  The F18A runs at 700 MIPS peak rate in a 180 nm process.  Instead of one or two in the FPGA like the ARMs in other FPGAs, there would be hundreds, each one running at some GHz.  

Rick C.

gnuarm.deletethisbit@gmail.com wrote:
> Certainly this would be like Forth, but the reality is I'm thinking of a
> Forth like CPU because they can be designed so simply.
> 
> The F18A stack processor designed by Charles Moore is used in the GA144
> chip.  There are 144 of them with unusual interconnections that allow the
> CPU to halt waiting for communications, saving power.  The CPU is so small
> that it could be included in an FPGA as what would be equivalent to a
> logic element.
> 
> In the same way that the other functional logic elements like the block
> RAMs and DSP blocks are used for custom functionality which requires the
> designer to program by whatever means is devised, these tiny CPUs would
> not need a high level language like C.  The code in them would be small
> enough to be considered "logic" and developed at the assembly level.

The problem this boils down to is programmability.

If you have a small core, you can therefore have lots of them.  But writing
software for and managing dozens or hundreds of cores is troublesome.  At
this level, you have enough headache with the inter-core communication that
you'd rather not throw a strange assembler-only core architecture into the
mix.  A core like this would need a simple inter-core programming model so
it's easy to reason about system behaviour (example: systolic arrays)

There's a certain merit in having a CPU as a building block, like a LAB,
BRAM or DSP block.  I'm not familiar with the literature in this space, but
it's the sort of thing that turns up at the 'FPGA' conference regularly
(keyword: CGRA).  That merely punts the issue to now being a tools problem -
the tools know how to make use of a DSP block, but how to make use of a CPU
block?  How to turn HDL into 'software'?  Can you chain the blocks together
to make wider logic?

I suppose there's also a niche at the ultra-cheap end of the spectrum - for
$1 gadgets with an 8051 because a 16 bit CPU would be too expensive (and a
Cortex M0 would have licence fees).  But if this is an ASIC then I don't
think there's a whole lot more to pay to get a C-compatible processor (even
in 8 bits).  And it's unclear how much speed penalty you'd pay for that.

How much code/data memory would you expect to have?  Would that dwarf the
size of your core?

Finally I can see the use as a 'state machine implementation engine' for say
a CPLD.  But for that you need tools (taking HDL or state-transition diagrams)
to allow the programmer to describe their state machine.  And your
competition is the regular HDL synthesiser which will just make it out of
flip flops.  I'm unclear how often you'd win in these circumstances.

And I can't really see 'interactive' as a feature - either you have only one
core, in which case you could equally hook up JTAG (or equivalent) to
something larger for interactive debugging, or you have many cores, in which
case I can't see how you'd interact sensibly with dozens at once.

Theo

On 19/03/19 00:13, gnuarm.deletethisbit@gmail.com wrote:
> Most of us have implemented small processors for logic operations that don't
> need to happen at high speed.  Simple CPUs can be built into an FPGA using a
> very small footprint much like the ALU blocks.  There are stack based
> processors that are very small, smaller than even a few kB of memory.
> 
> If they were easily programmable in something other than C would anyone be
> interested?  Or is a C compiler mandatory even for processors running very
> small programs?
> 
> I am picturing this not terribly unlike the sequencer I used many years ago
> on an I/O board for an array processor which had it's own assembler.  It was
> very simple and easy to use, but very much not a high level language.  This
> would have a language that was high level, just not C rather something
> extensible and simple to use and potentially interactive.
Who cares about yet another processor programmed in the same
old language. It would not have a *U*SP. In fact it would be
"back to the 80s" :)

However, if you want to make it interesting enough to pass
the elevator test, ensure it can do things that existing
systems find difficult.

You should have a look at how the XMOS hardware and software
complement each other, so that the combination allows hard
real time operation programming in multicore systems. (Hard
means guaranteed-by-design latencies between successive i/o
activities)

On 19/03/2019 09:32, gnuarm.deletethisbit@gmail.com wrote:
> On Tuesday, March 19, 2019 at 4:15:47 AM UTC-4, David Brown wrote:
>> On 19/03/2019 01:13, gnuarm.deletethisbit@gmail.com wrote:
>>> Most of us have implemented small processors for logic
>>> operations that don't need to happen at high speed.  Simple CPUs
>>> can be built into an FPGA using a very small footprint much like
>>> the ALU blocks. There are stack based processors that are very
>>> small, smaller than even a few kB of memory.
>>> 
>>> If they were easily programmable in something other than C would 
>>> anyone be interested?  Or is a C compiler mandatory even for 
>>> processors running very small programs?
>>> 
>>> I am picturing this not terribly unlike the sequencer I used
>>> many years ago on an I/O board for an array processor which had
>>> it's own assembler.  It was very simple and easy to use, but very
>>> much not a high level language.  This would have a language that
>>> was high level, just not C rather something extensible and simple
>>> to use and potentially interactive.
>>> 
>>> Rick C.
>>> 
>> 
>> If it is going to appeal to software developers, you need C.  And
>> it has to be reasonable, standard C, even if it is for small
>> devices - programmers are fed up with the pains needed for special
>> device-specific C on 8051, AVR, PIC, etc.  That does not
>> necessarily mean it has to be fast, but it should work with
>> standard language.  Having 16-bit size rather than 8-bit size makes
>> a huge difference to how programmers feel about the device - aim
>> for something like the msp430.
>> 
>> You might, however, want to look at extensions for CSP-style 
>> communication between cpus - something like XMOS XC.
>> 
>> If it is to appeal to hardware (FPGA) developers, C might not be
>> as essential.  Some other kind of high level language, perhaps
>> centred around state machines, might work.
>> 
>> But when I see "extensible, simple to use and potentially
>> interactive", I fear someone is thinking of Forth.  People who are
>> very used to Forth find it a great language - but you need to
>> understand that /nobody/ wants to learn it.  Most programmers would
>> rather work in assembler than Forth.  You can argue that this
>> attitude is irrational, and that Forth is not harder than other
>> languages - you might be right.  But that doesn't change matters.
> 
> Certainly this would be like Forth, but the reality is I'm thinking
> of a Forth like CPU because they can be designed so simply.

I appreciate that.

I can only tell you how /I/ would feel here, and let you use that for
what you think it is worth.  I don't claim to speak for all software
developers, but unless other people are giving you feedback too, then
this is the best you've got :-)  Remember, I am not trying to argue
about the pros and cons of different designs or languages, or challenge
you to persuade me of anything - I'm just showing you how software
developers might react to your design ideas.

> 
> The F18A stack processor designed by Charles Moore is used in the
> GA144 chip.  There are 144 of them with unusual interconnections that
> allow the CPU to halt waiting for communications, saving power.  The
> CPU is so small that it could be included in an FPGA as what would be
> equivalent to a logic element.

Yes, but look how popular the chip is - it is barely a blip in the
landscape.  There is no doubt that this is a technologically fascinating
device.  However, it is very difficult to program such chips - almost no
one is experienced with such multi-cpu arrangements, and the design
requires a completely different way of thinking from existing software
design.  Add to that a language that works backwards, and a syntax that
looks like the cat walked across the keyboard, and you have something
that has programmers running away.

My experience with Forth is small and outdated, but not non-existent.
I've worked with dozens of programming languages over the years - I've
studied CSP, programmed in Occam, functional programming languages, lots
of assemblies, a small amount of CPLD/FPGA work in various languages,
and many other kinds of coding.  (Most of my work for the past years has
been C, C++ and Python.)  I'm not afraid of learning new things.  But
when I looked at some of the examples for the GA144, three things struck
me.  One is that it was amazing how much they got on the device.
Another is to wonder about the limitations you get from the this sort of
architecture.  (That is a big turn-off with the XMOS.  It's
fantastically easy to make nice software-based peripherals using
hardware threads.  And fantastically easy to run out of hardware threads
before you've made the basic peripherals you get in a $0.50
microcontroller.)  And the third thing that comes across is how totally
and utterly incomprehensible the software design and the programming
examples are.  The GA144 is squarely in the category of technology that
is cool, impressive, and useless in the real world where developers have
to do a job, not play with toys.

Sure, it would be possible to learn this.  But there is no way I could
justify the investment in time and effort that would entail.

And there is no way I would want to go to a language with less safety,
poorer typing, weaker tools, harder testing, more limited static
checking than the development tools I can use now with C and C++.


> 
> In the same way that the other functional logic elements like the
> block RAMs and DSP blocks are used for custom functionality which
> requires the designer to program by whatever means is devised, these
> tiny CPUs would not need a high level language like C.  The code in
> them would be small enough to be considered "logic" and developed at
> the assembly level.

The modern way to use the DSP blocks on FPGA's is either with ready-made
logic blocks, code generator tools like Matlab, or C to hardware
converters.  They are not configured manually at a low level.  Even if
when they are generated directly from VHDL or Verilog, the developer
writes "x = y * z + w" with the required number of bits in each element,
and the tools turn that into whatever DSP blocks are needed.

The key thing you have to think about here, is who would use these tiny
cpus, and why.  Is there a reason for using a few of them scattered
around the device, programmed in assembly (or worse, Forth) ?  Why would
the developer want to do that instead of just adding another software
thread to the embedded ARM processor, where development is so much more
familiar?  Why would the hardware designer want them, instead of writing
a little state machine in the language of their choice (VHDL, Verilog,
System C, MyHDL, C-to-HDL compiler, whatever)?

I am missing the compelling use-cases here.  Yes, it is possible to make
small and simple cpu units with a stack machine architecture, and fit
lots of them in an FPGA.  But I don't see /why/ I would want them -
certainly not why they are better than alternatives, and worth the
learning curve.

> 
> People have mindsets about things and I believe this is one of them.

Exactly.  And you have a choice here - work with people with the
mindsets they have, or give /seriously/ compelling reasons why they
should invest in the time and effort needed to change those mindsets.
Wishful thinking is not the answer.

> The GA144 is not so easy to program because people want to use it for
> the sort of large programs they write for other fast CPUs.  

It is not easy to program because it is not easy to program.
Multi-threaded or multi-process software is harder than single-threaded
code.

The tools and language here for the GA144 - based on Forth - are two
generations behind the times.  They are totally unfamiliar to almost any
current software developer.

And yes, there is the question of what kind of software you would want
to write.  People either want to write small, dedicated software - in
which case they want a language that is familiar and they want to keep
the code simple.  Or they want bigger projects, reusing existing code -
in which case they /need/ a language that is standard.

Look at the GA144 site.  Apart from the immediate fact that it is pretty
much a dead site, and clearly a company that has failed to take off,
look at the examples.  A 10 Mb software Ethernet MAC ?  Who wants /that/
in software?  A PS/2 keyboard controller?  An MD5 hash generator running
in 16 cpus?  You can download a 100-line md5 function for C and run it
on any processor.


> In an
> FPGA a very fast processor can be part of the logic rather than an
> uber-controller riding herd over the whole chip.  But this would
> require designers to change their thinking of how to use CPUs.  The
> F18A runs at 700 MIPS peak rate in a 180 nm process.  Instead of one
> or two in the FPGA like the ARMs in other FPGAs, there would be
> hundreds, each one running at some GHz.
> 
It has long been established that lots of tiny processors running really
fast are far less use than a few big processors running really fast.
700 MIPS sounds marvellous, until you realise how simple and limited
each of these instructions is.

At each step here, you have been entirely right about what can be done.
 Yes, you can make small and simple processors - so small and simple
that you can have lots of them at high clock speeds.

And you have been right that using these would need a change in mindset,
programming language, and development practice to use them.

But nowhere do I see any good reason /why/.  No good use-cases.  If you
want to turn the software and FPGA development world on its head, you
need an extraordinarily good case for it.

On 19/03/19 10:08, Theo Markettos wrote:
> gnuarm.deletethisbit@gmail.com wrote:
>> Certainly this would be like Forth, but the reality is I'm thinking of a
>> Forth like CPU because they can be designed so simply.
>>
>> The F18A stack processor designed by Charles Moore is used in the GA144
>> chip.  There are 144 of them with unusual interconnections that allow the
>> CPU to halt waiting for communications, saving power.  The CPU is so small
>> that it could be included in an FPGA as what would be equivalent to a
>> logic element.
>>
>> In the same way that the other functional logic elements like the block
>> RAMs and DSP blocks are used for custom functionality which requires the
>> designer to program by whatever means is devised, these tiny CPUs would
>> not need a high level language like C.  The code in them would be small
>> enough to be considered "logic" and developed at the assembly level.
> 
> The problem this boils down to is programmability.
> 
> If you have a small core, you can therefore have lots of them.  But writing
> software for and managing dozens or hundreds of cores is troublesome.  At
> this level, you have enough headache with the inter-core communication that
> you'd rather not throw a strange assembler-only core architecture into the
> mix.  A core like this would need a simple inter-core programming model so
> it's easy to reason about system behaviour (example: systolic arrays)

Yup. The hardware is easy. Programming is painful, but there
are known techniques to control it...

There's an existing commercially successful set of products in
this domain. You get 32-core 4000MIPS processors, and the IDE
guarantees the hard real-time performance.

Programming uses a techniques created in the 70s, first
implemented in the 80s, and which continually reappear, e.g.
TI's DSP engines, Rust, Go etc.

Understand XMOS's xCORE processors and xC language, see how
they complement and support each other. I found the net result
stunningly easy to get working first time, without having to
continually read obscure errata!

On Tuesday, March 19, 2019 at 6:08:36 AM UTC-4, Theo Markettos wrote:
> gnuarm.deletethisbit@gmail.com wrote:
> > Certainly this would be like Forth, but the reality is I'm thinking of a
> > Forth like CPU because they can be designed so simply.
> > 
> > The F18A stack processor designed by Charles Moore is used in the GA144
> > chip.  There are 144 of them with unusual interconnections that allow the
> > CPU to halt waiting for communications, saving power.  The CPU is so small
> > that it could be included in an FPGA as what would be equivalent to a
> > logic element.
> > 
> > In the same way that the other functional logic elements like the block
> > RAMs and DSP blocks are used for custom functionality which requires the
> > designer to program by whatever means is devised, these tiny CPUs would
> > not need a high level language like C.  The code in them would be small
> > enough to be considered "logic" and developed at the assembly level.
> 
> The problem this boils down to is programmability.
> 
> If you have a small core, you can therefore have lots of them.  But writing
> software for and managing dozens or hundreds of cores is troublesome.  

So how do they design with the many other functional elements in an FPGA?  Is it really that hard to program the various logic functions in an FPGA because of the difficulty in defining their communications? 


> At
> this level, you have enough headache with the inter-core communication that
> you'd rather not throw a strange assembler-only core architecture into the
> mix.  

Wow!  Makes you wonder how FPGAs ever get designed at all.  

> A core like this would need a simple inter-core programming model so
> it's easy to reason about system behaviour (example: systolic arrays)

"Inter-core programming model", not sure what that means. 

I think you are overthinking this, much as people do when using large CPUs, not to say they are overthinking for those designs.  The whole point is that these CPUs would be used like logic blocks, not like CPUs.  Small, limited memory with programs written to be easy to debug and/or designed to simply work by being simple.  

I'm not sure how software people think really.  I worked with one guy to try to solve a problem and they were using a subroutine to do a memory access.  I suppose this was because it needed to be this specific code to get the access to work the way it needed to.  But then the guy kept looking at those five lines of code for some serious time.  It was pretty clear to me what it was doing.  Or he could have run the code or simulated it and looked to see what it did.  Actually that would have been a valid use of JTAG to single step through those five lines a few times.  But he just kept reading those five lines.  Wow!  


> There's a certain merit in having a CPU as a building block, like a LAB,
> BRAM or DSP block.  I'm not familiar with the literature in this space, but
> it's the sort of thing that turns up at the 'FPGA' conference regularly
> (keyword: CGRA).  That merely punts the issue to now being a tools problem -
> the tools know how to make use of a DSP block, but how to make use of a CPU
> block?  How to turn HDL into 'software'?  Can you chain the blocks together
> to make wider logic?

I don't see the difficulty.  I'm not so familiar with Verilog, but in VHDL you have sequential code.  It wouldn't be hard to program a CPU using VHDL I think.  If nothing else, there should be a way to code in assembler and embed the code similarly to what is done for ROM like functions in HDL. 


> I suppose there's also a niche at the ultra-cheap end of the spectrum - for
> $1 gadgets with an 8051 because a 16 bit CPU would be too expensive (and a
> Cortex M0 would have licence fees).  

I believe we have officially reached the point where $1 processors are 32 bit ARMs and you have to get below $0.50 before you consider needing 8 bit processors.  Not sure what this has to do with adding CPU functional elements to FPGAs. 


> But if this is an ASIC then I don't
> think there's a whole lot more to pay to get a C-compatible processor (even
> in 8 bits).  And it's unclear how much speed penalty you'd pay for that.

You are thinking of something totally different from using a CPU as logic.  Processors like ARMs are too large to have hundreds in an FPGA (unless it is a really large chip).  Their architectural capabilities are much more than what is required for this.  I suppose a small 8 bit CPU could be used, but why use such a tiny data path with such limited capability?  The architectural simplicity of a stack machine allows it to be designed to run very fast.  With speed comes a certain flexibility to keep up with the discrete logic.  


> How much code/data memory would you expect to have?  Would that dwarf the
> size of your core?

Small, very small.  Maybe 256 words of RAM.  Instructions on the F18A are only 5 bits and so pack four per in the 18 bit word.  The last instruction is only 3 bits wide expressing a subset of the 32 instructions otherwise coded for.  Round the word width up to 20 bits or even 32. 

I'm not sure what happens if this actual processor is shrunk from 180 nm to something like 20 nm.  It was highly optimized for the 180 nm process it is built in and it may require some tweaks to work well at smaller processes.  The F18A has no external clock and different instructions time differently with basic logic instruction running very fast and memory accesses taking more time.  You can think of it as an async processor. 


> Finally I can see the use as a 'state machine implementation engine' for say
> a CPLD.  But for that you need tools (taking HDL or state-transition diagrams)
> to allow the programmer to describe their state machine.  And your
> competition is the regular HDL synthesiser which will just make it out of
> flip flops.  I'm unclear how often you'd win in these circumstances.

If you have logic that is well implemented sequentially (at a very high speed, likely multiple GIPS) it will save a lot of room in the FPGA just as multipliers and other function blocks.  Hard cores are much more efficient and sequential code is most efficient in a CPU type design which leverages the size advantage of memory over logic. 


> And I can't really see 'interactive' as a feature - either you have only one
> core, in which case you could equally hook up JTAG (or equivalent) to
> something larger for interactive debugging, or you have many cores, in which
> case I can't see how you'd interact sensibly with dozens at once.

If you have to use JTAG to debug something like this you are pretty much doomed.  I haven't used JTAG for anything other than programming FPGAs in decades. 

In general FPGAs are 99.9% debugged in simulation.  The odd 0.1% requires pretty special thinking anyway and I don't find JTAG to be very useful.  My best debugging tool is wetware. 

The point of interactivity is to allow the code to be tested one definition at a time.  But then that is a Forth concept and I'm pretty sure not a familiar concept with most people. 

Rick C.

On Tuesday, March 19, 2019 at 2:13:38 AM UTC+2, gnuarm.del...@gmail.com wrote:
> Most of us have implemented small processors for logic operations that don't need to happen at high speed.  Simple CPUs can be built into an FPGA using a very small footprint much like the ALU blocks.  There are stack based processors that are very small, smaller than even a few kB of memory.  
> 
> If they were easily programmable in something other than C would anyone be interested?  Or is a C compiler mandatory even for processors running very small programs?  
> 
> I am picturing this not terribly unlike the sequencer I used many years ago on an I/O board for an array processor which had it's own assembler.  It was very simple and easy to use, but very much not a high level language.  This would have a language that was high level, just not C rather something extensible and simple to use and potentially interactive. 
> 
> Rick C.

It is clear that you have Forth in mind.
It is less clear why you don't say it straight.

On Tuesday, March 19, 2019 at 6:21:24 AM UTC-4, Tom Gardner wrote:
> On 19/03/19 00:13, gnuarm.deletethisbit@gmail.com wrote:
> > Most of us have implemented small processors for logic operations that don't
> > need to happen at high speed.  Simple CPUs can be built into an FPGA using a
> > very small footprint much like the ALU blocks.  There are stack based
> > processors that are very small, smaller than even a few kB of memory.
> > 
> > If they were easily programmable in something other than C would anyone be
> > interested?  Or is a C compiler mandatory even for processors running very
> > small programs?
> > 
> > I am picturing this not terribly unlike the sequencer I used many years ago
> > on an I/O board for an array processor which had it's own assembler.  It was
> > very simple and easy to use, but very much not a high level language.  This
> > would have a language that was high level, just not C rather something
> > extensible and simple to use and potentially interactive.
> Who cares about yet another processor programmed in the same
> old language. It would not have a *U*SP. In fact it would be
> "back to the 80s" :)

Sorry, I don't get what any of this means. 


> However, if you want to make it interesting enough to pass
> the elevator test, ensure it can do things that existing
> systems find difficult.
> 
> You should have a look at how the XMOS hardware and software
> complement each other, so that the combination allows hard
> real time operation programming in multicore systems. (Hard
> means guaranteed-by-design latencies between successive i/o
> activities)

Yeah I think the XMOS model is way more complex than what I am describing.  The XMOS processors are actually very complex and use lots of gates.  They also don't run all that fast.  Their claim to fame is to be able to communicate through shared memory as if the other CPUs were not there in the good way.  Otherwise they are conventional processors, programmed in conventional ways. 

The emphasis here is for the CPU to be nearly invisible as a CPU and much more like a function block.  You just have to "configure" the operation by writing a bit of code.  That's why 'C' is not desirable, it would be too cumbersome for small code blocks. 

Rick C.