Den 2019-03-29 kl. 01:17, skrev gnuarm.deletethisbit@gmail.com:> On Thursday, March 28, 2019 at 7:27:58 PM UTC-4, lasselangwad...@gmail.com wrote: >> fredag den 29. marts 2019 kl. 00.03.22 UTC+1 skrev gnuarm.de...@gmail.com: >>> On Thursday, March 28, 2019 at 6:16:28 PM UTC-4, lasselangwad...@gmail.com wrote: >>>> torsdag den 28. marts 2019 kl. 22.37.18 UTC+1 skrev gnuarm.de...@gmail.com: >>>>> On Thursday, March 28, 2019 at 4:49:25 PM UTC-4, A.P.Richelieu wrote: >>>>>> Den 2019-03-28 kl. 15:24, skrev Stef: >>>>>>> On 2019-03-28 Theo wrote in comp.arch.fpga: >>>>>>>> Stef <stef33d@yahooi-n-v-a-l-i-d.com.invalid> wrote: >>>>>>>>> Usually you use the vendor tools to generate a bitstream from an HDL >>>>>>>>> design. But are there options to generate these bitstreams during the >>>>>>>>> production cycle, in only a few seconds? Something like HDL + DATA = >>>>>>>>> BITSTREAM. And then burn the resulting bitsream in the device. >>>>>>>> >>>>>>>> Intel Quartus has an 'Update Memory Initialization File' step where you can >>>>>>>> change the memory contents of an existing project without recompiling. I >>>>>>>> don't know how much project scaffolding you'd need (you still need to run >>>>>>>> the Assembler step to generate bitfiles afterwards, so I don't think you can >>>>>>>> edit an existing bitfile). It's not super quick (maybe ten seconds for a >>>>>>>> Cyclone V) but better than a recompile. >>>>>>>> >>>>>>>> I think some of the Lattice parts have a user flash memory but I haven't >>>>>>>> used those: >>>>>>>> http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/UZ/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Devices.ashx?document_id=39086 >>>>>>>> >>>>>>>> I suppose another option is a small SPI/I2C flash chip and a CPLD that reads >>>>>>>> the contents in at powerup time. Or a NOR flash that you can program >>>>>>>> externally (but programming header with 8 address, 4 data, 3 control wires - >>>>>>>> might be too big) or another chip to drive them (I2C I/O expander for >>>>>>>> instance and a 3/4 pin header) >>>>>>>> >>>>>>>>> A device like the Lattice ispMACH 4000 seems a possible candidate. >>>>>>>> >>>>>>>> Does your old design have voltage requirements like 5V capability? >>>>>>> >>>>>>> The supply is 5V, but the interface on the reading device is 3V3 with 5V >>>>>>> tolerant IO. So adding 3V3 regulation for the memory power should work. >>>>>>> >>>>>>> Another limitation is that that the preferred programming interface is >>>>>>> through the available connections: Address (8), data (4), control (1 + >>>>>>> 1 tied to GND, and VCC rising to VPP). And there are 2 free pins that could >>>>>>> be used as well. >>>>>>> >>>>>>> This is a reason why parallel EEPROM (FLASH) is not an option. Those >>>>>>> devices all require access to all address and data to enter the programming >>>>>>> sequence. (or do you know a flash that does not require this?) >>>>>>> Or use a CPLD to generate those sequences? (based on the states of the free >>>>>>> pins?) >>>>>>> >>>>>> What is reading from the EPROM? >>>>>> What is the bus speed of the access? >>>>>> >>>>>> I would not be surprised, if you could not implement this with a >>>>>> microcontroller running at a decent clock frequency. >>>>>> >>>>>> A small Cortex-M0 chip like the ATSAMD10xxxx in a 20 - 32 pin package >>>>>> should be small >>>>>> >>>>>> The program will look like this: >>>>>> while (1) { >>>>>> port = memory[pins & 0xff]; >>>>>> oe = (pins & 0x100) ? ON : OFF; >>>>>> } >>>>>> >>>>>> AP >>>>> >>>>> I find it interesting that people often feel MCUs are simpler than programmable logic. What your program in particular lacks is the important part, allowing the contents of "memory[]" to be set at manufacturing time. I don't see the use of an MCU to be at all simple. In addition to the above, there is setup code that either needs to be written from scratch by reading the MCU data sheet (starting clocks, initialize I/O banks, brown out detectors, etc., etc...) or by starting with the standard startup code and paring out what is not needed or appropriate. >>>>> >>>>> To me, this is inordinately complex compared to the relatively trivial exercise of creating an HDL ROM which is about as complex as the code above and setting the details of the chosen I/O pins to be used. The only remaining issue is to use the vendor tool to initialize this ROM in the compiled code or even in the same way it is done now which I think is done by the board itself. >>>>> >>>>> Not only is the PLD method simpler, it provides a lot more flexibility. >>>> >>>> if the only thing in your toolbox it hammers, nailing things together always >>>> seem like the obvious choice >>>> >>>> at slow speed an mcu could be just as viable, and customizing the array could >>>> be as simple as patching the bin or hex file programmed into the part >>> >>> But you didn't address the additional setup required to write the code for the MCU. The ones I've used have a *lot* of features that need to be set up for the MCU to even run. MCU code is always a lot more complex to design with than HDL in my experience. >> >> >> so you have only used big MCUs with piles of peripherals and advanced features, small 8bitters are usually nothing like that >> >>> >>> "Patching" a hex file is not the way I want to manage configuration data. The PLD tools have already dealt with this issue. >>> >> >> doing exactly the same thing, replacing the data > > So there is a tool for patching the hex data? You don't need any startup code on your small 8 bitter? > > I think you are being a bit disingenuous about the patching issue. The MCU tools I've worked with would require quite a bit of work to replace data in binary code. >If you never used a micro, you may have a problem. If you have used a specific micro, then you are likely to have setup code. The ROM code is best expressed in C. const uint8_t memory[256] = { 0x00, 0x01, 0x02, 0x03, ... }; You get a state of the art C compiler/debugger from IAR free of charge for these types of applications. If you are not in a hurry, you can implement a bitbanged USART in three pins in the micro. You send an address, as an 8 bit byte, and the micro responds with the data. The Micro is going to be way cheaper than a programmable logic device if there is any volume at all behind such a request. You can also get much much smaller packages with micros than with programmable logic. AP
Replaceme EPROM by CPLD/FPGA
Started by ●March 28, 2019
Reply by ●March 29, 20192019-03-29
Reply by ●March 29, 20192019-03-29
On Friday, March 29, 2019 at 6:52:14 PM UTC-4, A.P.Richelieu wrote:> Den 2019-03-29 kl. 01:17, skrev gnuarm.deletethisbit@gmail.com: > > On Thursday, March 28, 2019 at 7:27:58 PM UTC-4, lasselangwad...@gmail.=com wrote:> >> fredag den 29. marts 2019 kl. 00.03.22 UTC+1 skrev gnuarm.de...@gmail.=com:> >>> On Thursday, March 28, 2019 at 6:16:28 PM UTC-4, lasselangwad...@gmai=l.com wrote:> >>>> torsdag den 28. marts 2019 kl. 22.37.18 UTC+1 skrev gnuarm.de...@gma=il.com:> >>>>> On Thursday, March 28, 2019 at 4:49:25 PM UTC-4, A.P.Richelieu wrot=e:> >>>>>> Den 2019-03-28 kl. 15:24, skrev Stef: > >>>>>>> On 2019-03-28 Theo wrote in comp.arch.fpga: > >>>>>>>> Stef <stef33d@yahooi-n-v-a-l-i-d.com.invalid> wrote: > >>>>>>>>> Usually you use the vendor tools to generate a bitstream from a=n HDL> >>>>>>>>> design. But are there options to generate these bitstreams duri=ng the> >>>>>>>>> production cycle, in only a few seconds? Something like HDL + D=ATA =3D> >>>>>>>>> BITSTREAM. And then burn the resulting bitsream in the device. > >>>>>>>> > >>>>>>>> Intel Quartus has an 'Update Memory Initialization File' step wh=ere you can> >>>>>>>> change the memory contents of an existing project without recomp=iling. I> >>>>>>>> don't know how much project scaffolding you'd need (you still ne=ed to run> >>>>>>>> the Assembler step to generate bitfiles afterwards, so I don't t=hink you can> >>>>>>>> edit an existing bitfile). It's not super quick (maybe ten seco=nds for a> >>>>>>>> Cyclone V) but better than a recompile. > >>>>>>>> > >>>>>>>> I think some of the Lattice parts have a user flash memory but I=haven't> >>>>>>>> used those: > >>>>>>>> http://www.latticesemi.com/-/media/LatticeSemi/Documents/Applica=tionNotes/UZ/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Device= s.ashx?document_id=3D39086> >>>>>>>> > >>>>>>>> I suppose another option is a small SPI/I2C flash chip and a CPL=D that reads> >>>>>>>> the contents in at powerup time. Or a NOR flash that you can pr=ogram> >>>>>>>> externally (but programming header with 8 address, 4 data, 3 con=trol wires -> >>>>>>>> might be too big) or another chip to drive them (I2C I/O expande=r for> >>>>>>>> instance and a 3/4 pin header) > >>>>>>>> > >>>>>>>>> A device like the Lattice ispMACH 4000 seems a possible candida=te.> >>>>>>>> > >>>>>>>> Does your old design have voltage requirements like 5V capabilit=y?> >>>>>>> > >>>>>>> The supply is 5V, but the interface on the reading device is 3V3 =with 5V> >>>>>>> tolerant IO. So adding 3V3 regulation for the memory power should=work.> >>>>>>> > >>>>>>> Another limitation is that that the preferred programming interfa=ce is> >>>>>>> through the available connections: Address (8), data (4), control=(1 +> >>>>>>> 1 tied to GND, and VCC rising to VPP). And there are 2 free pins =that could> >>>>>>> be used as well. > >>>>>>> > >>>>>>> This is a reason why parallel EEPROM (FLASH) is not an option. Th=ose> >>>>>>> devices all require access to all address and data to enter the p=rogramming> >>>>>>> sequence. (or do you know a flash that does not require this?) > >>>>>>> Or use a CPLD to generate those sequences? (based on the states o=f the free> >>>>>>> pins?) > >>>>>>> > >>>>>> What is reading from the EPROM? > >>>>>> What is the bus speed of the access? > >>>>>> > >>>>>> I would not be surprised, if you could not implement this with a > >>>>>> microcontroller running at a decent clock frequency. > >>>>>> > >>>>>> A small Cortex-M0 chip like the ATSAMD10xxxx in a 20 - 32 pin pack=age> >>>>>> should be small > >>>>>> > >>>>>> The program will look like this: > >>>>>> while (1) { > >>>>>> port =3D memory[pins & 0xff]; > >>>>>> oe =3D (pins & 0x100) ? ON : OFF; > >>>>>> } > >>>>>> > >>>>>> AP > >>>>> > >>>>> I find it interesting that people often feel MCUs are simpler than =programmable logic. What your program in particular lacks is the important= part, allowing the contents of "memory[]" to be set at manufacturing time.= I don't see the use of an MCU to be at all simple. In addition to the ab= ove, there is setup code that either needs to be written from scratch by re= ading the MCU data sheet (starting clocks, initialize I/O banks, brown out = detectors, etc., etc...) or by starting with the standard startup code and = paring out what is not needed or appropriate.> >>>>> > >>>>> To me, this is inordinately complex compared to the relatively triv=ial exercise of creating an HDL ROM which is about as complex as the code a= bove and setting the details of the chosen I/O pins to be used. The only r= emaining issue is to use the vendor tool to initialize this ROM in the comp= iled code or even in the same way it is done now which I think is done by t= he board itself.> >>>>> > >>>>> Not only is the PLD method simpler, it provides a lot more flexibil=ity.> >>>> > >>>> if the only thing in your toolbox it hammers, nailing things togethe=r always> >>>> seem like the obvious choice > >>>> > >>>> at slow speed an mcu could be just as viable, and customizing the ar=ray could> >>>> be as simple as patching the bin or hex file programmed into the par=t> >>> > >>> But you didn't address the additional setup required to write the cod=e for the MCU. The ones I've used have a *lot* of features that need to be= set up for the MCU to even run. MCU code is always a lot more complex to = design with than HDL in my experience.> >> > >> > >> so you have only used big MCUs with piles of peripherals and advanced =features, small 8bitters are usually nothing like that> >> > >>> > >>> "Patching" a hex file is not the way I want to manage configuration d=ata. The PLD tools have already dealt with this issue.> >>> > >> > >> doing exactly the same thing, replacing the data > >=20 > > So there is a tool for patching the hex data? You don't need any start=up code on your small 8 bitter?> >=20 > > I think you are being a bit disingenuous about the patching issue. The=MCU tools I've worked with would require quite a bit of work to replace da= ta in binary code.> >=20 > If you never used a micro, you may have a problem. > If you have used a specific micro, then you are likely to have setup code=.>=20 > The ROM code is best expressed in C. > const uint8_t memory[256] =3D { > 0x00, 0x01, 0x02, 0x03, ... > }; >=20 > You get a state of the art C compiler/debugger from IAR free of charge > for these types of applications. >=20 > If you are not in a hurry, you can implement a bitbanged USART in three==20> pins in the micro. > You send an address, as an 8 bit byte, and the micro responds with the da=ta.>=20 > The Micro is going to be way cheaper than a programmable logic device > if there is any volume at all behind such a request. >=20 > You can also get much much smaller packages with micros than with=20 > programmable logic.Not if the design is pin defined. This design can't be done with an 8 pin = package. =20 Cost depends on many things and some FPGAs are very inexpensive. Having th= e simplest production solution is a great start. So far FPGAs are the only= solution that actually provides a clear and simple method of being program= med with the configuration data in production without issues. But I should= n't say that because I don't truly understand all the issues the OP has. I= do know that the FPGA will handle them all as presently understood. The M= CU will require some work to make that happen I believe.=20 --=20 Rick C. --- Get a 1,000 miles of free Supercharging --- Tesla referral code - https://ts.la/richard11209
Reply by ●March 30, 20192019-03-30
Den 2019-03-30 kl. 02:48, skrev gnuarm.deletethisbit@gmail.com:> On Friday, March 29, 2019 at 6:52:14 PM UTC-4, A.P.Richelieu wrote: >> Den 2019-03-29 kl. 01:17, skrev gnuarm.deletethisbit@gmail.com: >>> On Thursday, March 28, 2019 at 7:27:58 PM UTC-4, lasselangwad...@gmail.com wrote: >>>> fredag den 29. marts 2019 kl. 00.03.22 UTC+1 skrev gnuarm.de...@gmail.com: >>>>> On Thursday, March 28, 2019 at 6:16:28 PM UTC-4, lasselangwad...@gmail.com wrote: >>>>>> torsdag den 28. marts 2019 kl. 22.37.18 UTC+1 skrev gnuarm.de...@gmail.com: >>>>>>> On Thursday, March 28, 2019 at 4:49:25 PM UTC-4, A.P.Richelieu wrote: >>>>>>>> Den 2019-03-28 kl. 15:24, skrev Stef: >>>>>>>>> On 2019-03-28 Theo wrote in comp.arch.fpga: >>>>>>>>>> Stef <stef33d@yahooi-n-v-a-l-i-d.com.invalid> wrote: >>>>>>>>>>> Usually you use the vendor tools to generate a bitstream from an HDL >>>>>>>>>>> design. But are there options to generate these bitstreams during the >>>>>>>>>>> production cycle, in only a few seconds? Something like HDL + DATA = >>>>>>>>>>> BITSTREAM. And then burn the resulting bitsream in the device. >>>>>>>>>> >>>>>>>>>> Intel Quartus has an 'Update Memory Initialization File' step where you can >>>>>>>>>> change the memory contents of an existing project without recompiling. I >>>>>>>>>> don't know how much project scaffolding you'd need (you still need to run >>>>>>>>>> the Assembler step to generate bitfiles afterwards, so I don't think you can >>>>>>>>>> edit an existing bitfile). It's not super quick (maybe ten seconds for a >>>>>>>>>> Cyclone V) but better than a recompile. >>>>>>>>>> >>>>>>>>>> I think some of the Lattice parts have a user flash memory but I haven't >>>>>>>>>> used those: >>>>>>>>>> http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/UZ/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Devices.ashx?document_id=39086 >>>>>>>>>> >>>>>>>>>> I suppose another option is a small SPI/I2C flash chip and a CPLD that reads >>>>>>>>>> the contents in at powerup time. Or a NOR flash that you can program >>>>>>>>>> externally (but programming header with 8 address, 4 data, 3 control wires - >>>>>>>>>> might be too big) or another chip to drive them (I2C I/O expander for >>>>>>>>>> instance and a 3/4 pin header) >>>>>>>>>> >>>>>>>>>>> A device like the Lattice ispMACH 4000 seems a possible candidate. >>>>>>>>>> >>>>>>>>>> Does your old design have voltage requirements like 5V capability? >>>>>>>>> >>>>>>>>> The supply is 5V, but the interface on the reading device is 3V3 with 5V >>>>>>>>> tolerant IO. So adding 3V3 regulation for the memory power should work. >>>>>>>>> >>>>>>>>> Another limitation is that that the preferred programming interface is >>>>>>>>> through the available connections: Address (8), data (4), control (1 + >>>>>>>>> 1 tied to GND, and VCC rising to VPP). And there are 2 free pins that could >>>>>>>>> be used as well. >>>>>>>>> >>>>>>>>> This is a reason why parallel EEPROM (FLASH) is not an option. Those >>>>>>>>> devices all require access to all address and data to enter the programming >>>>>>>>> sequence. (or do you know a flash that does not require this?) >>>>>>>>> Or use a CPLD to generate those sequences? (based on the states of the free >>>>>>>>> pins?) >>>>>>>>> >>>>>>>> What is reading from the EPROM? >>>>>>>> What is the bus speed of the access? >>>>>>>> >>>>>>>> I would not be surprised, if you could not implement this with a >>>>>>>> microcontroller running at a decent clock frequency. >>>>>>>> >>>>>>>> A small Cortex-M0 chip like the ATSAMD10xxxx in a 20 - 32 pin package >>>>>>>> should be small >>>>>>>> >>>>>>>> The program will look like this: >>>>>>>> while (1) { >>>>>>>> port = memory[pins & 0xff]; >>>>>>>> oe = (pins & 0x100) ? ON : OFF; >>>>>>>> } >>>>>>>> >>>>>>>> AP >>>>>>> >>>>>>> I find it interesting that people often feel MCUs are simpler than programmable logic. What your program in particular lacks is the important part, allowing the contents of "memory[]" to be set at manufacturing time. I don't see the use of an MCU to be at all simple. In addition to the above, there is setup code that either needs to be written from scratch by reading the MCU data sheet (starting clocks, initialize I/O banks, brown out detectors, etc., etc...) or by starting with the standard startup code and paring out what is not needed or appropriate. >>>>>>> >>>>>>> To me, this is inordinately complex compared to the relatively trivial exercise of creating an HDL ROM which is about as complex as the code above and setting the details of the chosen I/O pins to be used. The only remaining issue is to use the vendor tool to initialize this ROM in the compiled code or even in the same way it is done now which I think is done by the board itself. >>>>>>> >>>>>>> Not only is the PLD method simpler, it provides a lot more flexibility. >>>>>> >>>>>> if the only thing in your toolbox it hammers, nailing things together always >>>>>> seem like the obvious choice >>>>>> >>>>>> at slow speed an mcu could be just as viable, and customizing the array could >>>>>> be as simple as patching the bin or hex file programmed into the part >>>>> >>>>> But you didn't address the additional setup required to write the code for the MCU. The ones I've used have a *lot* of features that need to be set up for the MCU to even run. MCU code is always a lot more complex to design with than HDL in my experience. >>>> >>>> >>>> so you have only used big MCUs with piles of peripherals and advanced features, small 8bitters are usually nothing like that >>>> >>>>> >>>>> "Patching" a hex file is not the way I want to manage configuration data. The PLD tools have already dealt with this issue. >>>>> >>>> >>>> doing exactly the same thing, replacing the data >>> >>> So there is a tool for patching the hex data? You don't need any startup code on your small 8 bitter? >>> >>> I think you are being a bit disingenuous about the patching issue. The MCU tools I've worked with would require quite a bit of work to replace data in binary code. >>> >> If you never used a micro, you may have a problem. >> If you have used a specific micro, then you are likely to have setup code. >> >> The ROM code is best expressed in C. >> const uint8_t memory[256] = { >> 0x00, 0x01, 0x02, 0x03, ... >> }; >> >> You get a state of the art C compiler/debugger from IAR free of charge >> for these types of applications. >> >> If you are not in a hurry, you can implement a bitbanged USART in three >> pins in the micro. >> You send an address, as an 8 bit byte, and the micro responds with the data. >> >> The Micro is going to be way cheaper than a programmable logic device >> if there is any volume at all behind such a request. >> >> You can also get much much smaller packages with micros than with >> programmable logic. > > Not if the design is pin defined. This design can't be done with an 8 pin package. > > Cost depends on many things and some FPGAs are very inexpensive. Having the simplest production solution is a great start. So far FPGAs are the only solution that actually provides a clear and simple method of being programmed with the configuration data in production without issues. But I shouldn't say that because I don't truly understand all the issues the OP has. I do know that the FPGA will handle them all as presently understood. The MCU will require some work to make that happen I believe. >The configuration file is a simple text file which gets included in the build. It is easily generated from a hex file, if that is a need. You can program the microcontroller and the FPGA before you mount it to the PCB. Otherwise you program both using JTAG. There is ZERO issues in programming a micro. It is well known thing. There will be some fallout with BOTH. If there is a need to update the contents in the field, you can do so using a serial port = 2 pin. With a need for 13 I/Os, for the ROM interface, a 24 pin QFN package (4 x 4 mm) should do. Smallest FPGA is 3 x the price. It is going to cost around $1.25 @ 1 piece @ Digikey. The smallest FPGA is 3 x the price. The power consumption is going to be a fraction of that of an FPGA. The only thing that needs to be checked if the solution is fast enough. AP
Reply by ●March 30, 20192019-03-30
On Saturday, March 30, 2019 at 12:54:36 AM UTC-4, A.P.Richelieu wrote:> Den 2019-03-30 kl. 02:48, skrev gnuarm.deletethisbit@gmail.com: > > On Friday, March 29, 2019 at 6:52:14 PM UTC-4, A.P.Richelieu wrote: > >> Den 2019-03-29 kl. 01:17, skrev gnuarm.deletethisbit@gmail.com: > >>> On Thursday, March 28, 2019 at 7:27:58 PM UTC-4, lasselangwad...@gmail.com wrote: > >>>> fredag den 29. marts 2019 kl. 00.03.22 UTC+1 skrev gnuarm.de...@gmail.com: > >>>>> On Thursday, March 28, 2019 at 6:16:28 PM UTC-4, lasselangwad...@gmail.com wrote: > >>>>>> torsdag den 28. marts 2019 kl. 22.37.18 UTC+1 skrev gnuarm.de...@gmail.com: > >>>>>>> On Thursday, March 28, 2019 at 4:49:25 PM UTC-4, A.P.Richelieu wrote: > >>>>>>>> Den 2019-03-28 kl. 15:24, skrev Stef: > >>>>>>>>> On 2019-03-28 Theo wrote in comp.arch.fpga: > >>>>>>>>>> Stef <stef33d@yahooi-n-v-a-l-i-d.com.invalid> wrote: > >>>>>>>>>>> Usually you use the vendor tools to generate a bitstream from an HDL > >>>>>>>>>>> design. But are there options to generate these bitstreams during the > >>>>>>>>>>> production cycle, in only a few seconds? Something like HDL + DATA = > >>>>>>>>>>> BITSTREAM. And then burn the resulting bitsream in the device. > >>>>>>>>>> > >>>>>>>>>> Intel Quartus has an 'Update Memory Initialization File' step where you can > >>>>>>>>>> change the memory contents of an existing project without recompiling. I > >>>>>>>>>> don't know how much project scaffolding you'd need (you still need to run > >>>>>>>>>> the Assembler step to generate bitfiles afterwards, so I don't think you can > >>>>>>>>>> edit an existing bitfile). It's not super quick (maybe ten seconds for a > >>>>>>>>>> Cyclone V) but better than a recompile. > >>>>>>>>>> > >>>>>>>>>> I think some of the Lattice parts have a user flash memory but I haven't > >>>>>>>>>> used those: > >>>>>>>>>> http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/UZ/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Devices.ashx?document_id=39086 > >>>>>>>>>> > >>>>>>>>>> I suppose another option is a small SPI/I2C flash chip and a CPLD that reads > >>>>>>>>>> the contents in at powerup time. Or a NOR flash that you can program > >>>>>>>>>> externally (but programming header with 8 address, 4 data, 3 control wires - > >>>>>>>>>> might be too big) or another chip to drive them (I2C I/O expander for > >>>>>>>>>> instance and a 3/4 pin header) > >>>>>>>>>> > >>>>>>>>>>> A device like the Lattice ispMACH 4000 seems a possible candidate. > >>>>>>>>>> > >>>>>>>>>> Does your old design have voltage requirements like 5V capability? > >>>>>>>>> > >>>>>>>>> The supply is 5V, but the interface on the reading device is 3V3 with 5V > >>>>>>>>> tolerant IO. So adding 3V3 regulation for the memory power should work. > >>>>>>>>> > >>>>>>>>> Another limitation is that that the preferred programming interface is > >>>>>>>>> through the available connections: Address (8), data (4), control (1 + > >>>>>>>>> 1 tied to GND, and VCC rising to VPP). And there are 2 free pins that could > >>>>>>>>> be used as well. > >>>>>>>>> > >>>>>>>>> This is a reason why parallel EEPROM (FLASH) is not an option. Those > >>>>>>>>> devices all require access to all address and data to enter the programming > >>>>>>>>> sequence. (or do you know a flash that does not require this?) > >>>>>>>>> Or use a CPLD to generate those sequences? (based on the states of the free > >>>>>>>>> pins?) > >>>>>>>>> > >>>>>>>> What is reading from the EPROM? > >>>>>>>> What is the bus speed of the access? > >>>>>>>> > >>>>>>>> I would not be surprised, if you could not implement this with a > >>>>>>>> microcontroller running at a decent clock frequency. > >>>>>>>> > >>>>>>>> A small Cortex-M0 chip like the ATSAMD10xxxx in a 20 - 32 pin package > >>>>>>>> should be small > >>>>>>>> > >>>>>>>> The program will look like this: > >>>>>>>> while (1) { > >>>>>>>> port = memory[pins & 0xff]; > >>>>>>>> oe = (pins & 0x100) ? ON : OFF; > >>>>>>>> } > >>>>>>>> > >>>>>>>> AP > >>>>>>> > >>>>>>> I find it interesting that people often feel MCUs are simpler than programmable logic. What your program in particular lacks is the important part, allowing the contents of "memory[]" to be set at manufacturing time. I don't see the use of an MCU to be at all simple. In addition to the above, there is setup code that either needs to be written from scratch by reading the MCU data sheet (starting clocks, initialize I/O banks, brown out detectors, etc., etc...) or by starting with the standard startup code and paring out what is not needed or appropriate. > >>>>>>> > >>>>>>> To me, this is inordinately complex compared to the relatively trivial exercise of creating an HDL ROM which is about as complex as the code above and setting the details of the chosen I/O pins to be used. The only remaining issue is to use the vendor tool to initialize this ROM in the compiled code or even in the same way it is done now which I think is done by the board itself. > >>>>>>> > >>>>>>> Not only is the PLD method simpler, it provides a lot more flexibility. > >>>>>> > >>>>>> if the only thing in your toolbox it hammers, nailing things together always > >>>>>> seem like the obvious choice > >>>>>> > >>>>>> at slow speed an mcu could be just as viable, and customizing the array could > >>>>>> be as simple as patching the bin or hex file programmed into the part > >>>>> > >>>>> But you didn't address the additional setup required to write the code for the MCU. The ones I've used have a *lot* of features that need to be set up for the MCU to even run. MCU code is always a lot more complex to design with than HDL in my experience. > >>>> > >>>> > >>>> so you have only used big MCUs with piles of peripherals and advanced features, small 8bitters are usually nothing like that > >>>> > >>>>> > >>>>> "Patching" a hex file is not the way I want to manage configuration data. The PLD tools have already dealt with this issue. > >>>>> > >>>> > >>>> doing exactly the same thing, replacing the data > >>> > >>> So there is a tool for patching the hex data? You don't need any startup code on your small 8 bitter? > >>> > >>> I think you are being a bit disingenuous about the patching issue. The MCU tools I've worked with would require quite a bit of work to replace data in binary code. > >>> > >> If you never used a micro, you may have a problem. > >> If you have used a specific micro, then you are likely to have setup code. > >> > >> The ROM code is best expressed in C. > >> const uint8_t memory[256] = { > >> 0x00, 0x01, 0x02, 0x03, ... > >> }; > >> > >> You get a state of the art C compiler/debugger from IAR free of charge > >> for these types of applications. > >> > >> If you are not in a hurry, you can implement a bitbanged USART in three > >> pins in the micro. > >> You send an address, as an 8 bit byte, and the micro responds with the data. > >> > >> The Micro is going to be way cheaper than a programmable logic device > >> if there is any volume at all behind such a request. > >> > >> You can also get much much smaller packages with micros than with > >> programmable logic. > > > > Not if the design is pin defined. This design can't be done with an 8 pin package. > > > > Cost depends on many things and some FPGAs are very inexpensive. Having the simplest production solution is a great start. So far FPGAs are the only solution that actually provides a clear and simple method of being programmed with the configuration data in production without issues. But I shouldn't say that because I don't truly understand all the issues the OP has. I do know that the FPGA will handle them all as presently understood. The MCU will require some work to make that happen I believe. > > > > The configuration file is a simple text file which gets included in the > build. It is easily generated from a hex file, if that is a need. > You can program the microcontroller and the FPGA before you mount it to > the PCB. Otherwise you program both using JTAG. > There is ZERO issues in programming a micro. It is well known thing. > There will be some fallout with BOTH. > > If there is a need to update the contents in the field, you can do so > using a serial port = 2 pin. > > With a need for 13 I/Os, for the ROM interface, a 24 pin QFN package (4 > x 4 mm) should do. Smallest FPGA is 3 x the price. > > It is going to cost around $1.25 @ 1 piece @ Digikey. > The smallest FPGA is 3 x the price. > The power consumption is going to be a fraction of that of an FPGA. > > The only thing that needs to be checked if the solution is fast enough.The issue is that the programming file needs to be modified with calibration data for each device being programmed. This process is well defined for FPGAs since it is common to need to load block rams or in this case User Flash. In addition there are particular methods of loading the User Flash. The point is the loading of configuration data can be easily integrated into the typical programming process for the FPGA. This is not as straightforward for the MCU where you need to perform a build rather than just loading the configuration data. Your information about FPGAs is not so current, especially the power consumption. You clearly have not worked with the lower power devices which are available. There are devices that have double digit microamp power levels if not being clocked at high rates. The devices I have pointed to are available in QFN packages in addition to very tiny chip scale packages. FPGA packaging is one of my pet peaves. The focus in smaller FPGAs seems to be package size to fit mobile apps. So while there are very tiny packages available, they don't suit my apps. But you can't say small packages aren't available. -- Rick C. --+ Get a 1,000 miles of free Supercharging --+ Tesla referral code - https://ts.la/richard11209
Reply by ●March 30, 20192019-03-30
Den 2019-03-30 kl. 08:12, skrev gnuarm.deletethisbit@gmail.com:> On Saturday, March 30, 2019 at 12:54:36 AM UTC-4, A.P.Richelieu wrote: >> Den 2019-03-30 kl. 02:48, skrev gnuarm.deletethisbit@gmail.com: >>> On Friday, March 29, 2019 at 6:52:14 PM UTC-4, A.P.Richelieu wrote: >>>> Den 2019-03-29 kl. 01:17, skrev gnuarm.deletethisbit@gmail.com: >>>>> On Thursday, March 28, 2019 at 7:27:58 PM UTC-4, lasselangwad...@gmail.com wrote: >>>>>> fredag den 29. marts 2019 kl. 00.03.22 UTC+1 skrev gnuarm.de...@gmail.com: >>>>>>> On Thursday, March 28, 2019 at 6:16:28 PM UTC-4, lasselangwad...@gmail.com wrote: >>>>>>>> torsdag den 28. marts 2019 kl. 22.37.18 UTC+1 skrev gnuarm.de...@gmail.com: >>>>>>>>> On Thursday, March 28, 2019 at 4:49:25 PM UTC-4, A.P.Richelieu wrote: >>>>>>>>>> Den 2019-03-28 kl. 15:24, skrev Stef: >>>>>>>>>>> On 2019-03-28 Theo wrote in comp.arch.fpga: >>>>>>>>>>>> Stef <stef33d@yahooi-n-v-a-l-i-d.com.invalid> wrote: >>>>>>>>>>>>> Usually you use the vendor tools to generate a bitstream from an HDL >>>>>>>>>>>>> design. But are there options to generate these bitstreams during the >>>>>>>>>>>>> production cycle, in only a few seconds? Something like HDL + DATA = >>>>>>>>>>>>> BITSTREAM. And then burn the resulting bitsream in the device. >>>>>>>>>>>> >>>>>>>>>>>> Intel Quartus has an 'Update Memory Initialization File' step where you can >>>>>>>>>>>> change the memory contents of an existing project without recompiling. I >>>>>>>>>>>> don't know how much project scaffolding you'd need (you still need to run >>>>>>>>>>>> the Assembler step to generate bitfiles afterwards, so I don't think you can >>>>>>>>>>>> edit an existing bitfile). It's not super quick (maybe ten seconds for a >>>>>>>>>>>> Cyclone V) but better than a recompile. >>>>>>>>>>>> >>>>>>>>>>>> I think some of the Lattice parts have a user flash memory but I haven't >>>>>>>>>>>> used those: >>>>>>>>>>>> http://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/UZ/UsingUserFlashMemoryandHardenedControlFunctionsinMachXO2Devices.ashx?document_id=39086 >>>>>>>>>>>> >>>>>>>>>>>> I suppose another option is a small SPI/I2C flash chip and a CPLD that reads >>>>>>>>>>>> the contents in at powerup time. Or a NOR flash that you can program >>>>>>>>>>>> externally (but programming header with 8 address, 4 data, 3 control wires - >>>>>>>>>>>> might be too big) or another chip to drive them (I2C I/O expander for >>>>>>>>>>>> instance and a 3/4 pin header) >>>>>>>>>>>> >>>>>>>>>>>>> A device like the Lattice ispMACH 4000 seems a possible candidate. >>>>>>>>>>>> >>>>>>>>>>>> Does your old design have voltage requirements like 5V capability? >>>>>>>>>>> >>>>>>>>>>> The supply is 5V, but the interface on the reading device is 3V3 with 5V >>>>>>>>>>> tolerant IO. So adding 3V3 regulation for the memory power should work. >>>>>>>>>>> >>>>>>>>>>> Another limitation is that that the preferred programming interface is >>>>>>>>>>> through the available connections: Address (8), data (4), control (1 + >>>>>>>>>>> 1 tied to GND, and VCC rising to VPP). And there are 2 free pins that could >>>>>>>>>>> be used as well. >>>>>>>>>>> >>>>>>>>>>> This is a reason why parallel EEPROM (FLASH) is not an option. Those >>>>>>>>>>> devices all require access to all address and data to enter the programming >>>>>>>>>>> sequence. (or do you know a flash that does not require this?) >>>>>>>>>>> Or use a CPLD to generate those sequences? (based on the states of the free >>>>>>>>>>> pins?) >>>>>>>>>>> >>>>>>>>>> What is reading from the EPROM? >>>>>>>>>> What is the bus speed of the access? >>>>>>>>>> >>>>>>>>>> I would not be surprised, if you could not implement this with a >>>>>>>>>> microcontroller running at a decent clock frequency. >>>>>>>>>> >>>>>>>>>> A small Cortex-M0 chip like the ATSAMD10xxxx in a 20 - 32 pin package >>>>>>>>>> should be small >>>>>>>>>> >>>>>>>>>> The program will look like this: >>>>>>>>>> while (1) { >>>>>>>>>> port = memory[pins & 0xff]; >>>>>>>>>> oe = (pins & 0x100) ? ON : OFF; >>>>>>>>>> } >>>>>>>>>> >>>>>>>>>> AP >>>>>>>>> >>>>>>>>> I find it interesting that people often feel MCUs are simpler than programmable logic. What your program in particular lacks is the important part, allowing the contents of "memory[]" to be set at manufacturing time. I don't see the use of an MCU to be at all simple. In addition to the above, there is setup code that either needs to be written from scratch by reading the MCU data sheet (starting clocks, initialize I/O banks, brown out detectors, etc., etc...) or by starting with the standard startup code and paring out what is not needed or appropriate. >>>>>>>>> >>>>>>>>> To me, this is inordinately complex compared to the relatively trivial exercise of creating an HDL ROM which is about as complex as the code above and setting the details of the chosen I/O pins to be used. The only remaining issue is to use the vendor tool to initialize this ROM in the compiled code or even in the same way it is done now which I think is done by the board itself. >>>>>>>>> >>>>>>>>> Not only is the PLD method simpler, it provides a lot more flexibility. >>>>>>>> >>>>>>>> if the only thing in your toolbox it hammers, nailing things together always >>>>>>>> seem like the obvious choice >>>>>>>> >>>>>>>> at slow speed an mcu could be just as viable, and customizing the array could >>>>>>>> be as simple as patching the bin or hex file programmed into the part >>>>>>> >>>>>>> But you didn't address the additional setup required to write the code for the MCU. The ones I've used have a *lot* of features that need to be set up for the MCU to even run. MCU code is always a lot more complex to design with than HDL in my experience. >>>>>> >>>>>> >>>>>> so you have only used big MCUs with piles of peripherals and advanced features, small 8bitters are usually nothing like that >>>>>> >>>>>>> >>>>>>> "Patching" a hex file is not the way I want to manage configuration data. The PLD tools have already dealt with this issue. >>>>>>> >>>>>> >>>>>> doing exactly the same thing, replacing the data >>>>> >>>>> So there is a tool for patching the hex data? You don't need any startup code on your small 8 bitter? >>>>> >>>>> I think you are being a bit disingenuous about the patching issue. The MCU tools I've worked with would require quite a bit of work to replace data in binary code. >>>>> >>>> If you never used a micro, you may have a problem. >>>> If you have used a specific micro, then you are likely to have setup code. >>>> >>>> The ROM code is best expressed in C. >>>> const uint8_t memory[256] = { >>>> 0x00, 0x01, 0x02, 0x03, ... >>>> }; >>>> >>>> You get a state of the art C compiler/debugger from IAR free of charge >>>> for these types of applications. >>>> >>>> If you are not in a hurry, you can implement a bitbanged USART in three >>>> pins in the micro. >>>> You send an address, as an 8 bit byte, and the micro responds with the data. >>>> >>>> The Micro is going to be way cheaper than a programmable logic device >>>> if there is any volume at all behind such a request. >>>> >>>> You can also get much much smaller packages with micros than with >>>> programmable logic. >>> >>> Not if the design is pin defined. This design can't be done with an 8 pin package. >>> >>> Cost depends on many things and some FPGAs are very inexpensive. Having the simplest production solution is a great start. So far FPGAs are the only solution that actually provides a clear and simple method of being programmed with the configuration data in production without issues. But I shouldn't say that because I don't truly understand all the issues the OP has. I do know that the FPGA will handle them all as presently understood. The MCU will require some work to make that happen I believe. >>> >> >> The configuration file is a simple text file which gets included in the >> build. It is easily generated from a hex file, if that is a need. >> You can program the microcontroller and the FPGA before you mount it to >> the PCB. Otherwise you program both using JTAG. >> There is ZERO issues in programming a micro. It is well known thing. >> There will be some fallout with BOTH. >> >> If there is a need to update the contents in the field, you can do so >> using a serial port = 2 pin. >> >> With a need for 13 I/Os, for the ROM interface, a 24 pin QFN package (4 >> x 4 mm) should do. Smallest FPGA is 3 x the price. >> >> It is going to cost around $1.25 @ 1 piece @ Digikey. >> The smallest FPGA is 3 x the price. >> The power consumption is going to be a fraction of that of an FPGA. >> >> The only thing that needs to be checked if the solution is fast enough. > > The issue is that the programming file needs to be modified with calibration data for each device being programmed. This process is well defined for FPGAs since it is common to need to load block rams or in this case User Flash. In addition there are particular methods of loading the User Flash. > > The point is the loading of configuration data can be easily integrated into the typical programming process for the FPGA. This is not as straightforward for the MCU where you need to perform a build rather than just loading the configuration data. > > Your information about FPGAs is not so current, especially the power consumption. You clearly have not worked with the lower power devices which are available. There are devices that have double digit microamp power levels if not being clocked at high rates. The devices I have pointed to are available in QFN packages in addition to very tiny chip scale packages. > > FPGA packaging is one of my pet peaves. The focus in smaller FPGAs seems to be package size to fit mobile apps. So while there are very tiny packages available, they don't suit my apps. But you can't say small packages aren't available. >Once you have programmed the microcontroller, you use a write pin to program the part, and a read pin to read out the part. These things can be connected to DMA, for quite high speed. Since the reads were "slow", I bet this is good enough. Piece of cake. The build to add an additional memory array of 128 bytes takes a fraction of a second. It is not complex. It is well known technology. To say that this is not straightforward shows that you know little about MCUs. AP
Reply by ●March 30, 20192019-03-30
In article <q7nbpc$1v9l$1@gioia.aioe.org>, aprichelieu@gmail.com says...> > Once you have programmed the microcontroller, you use a write pin to > program the part, and a read pin to read out the part. > These things can be connected to DMA, for quite high speed. > Since the reads were "slow", I bet this is good enough. > Piece of cake. > > The build to add an additional memory array of 128 bytes takes a > fraction of a second. It is not complex. It is well known technology. > To say that this is not straightforward shows that you know little about > MCUs. > > AP >The first thing that went through my mind when I saw the original post was "microchip PIC" - the size of a full stop. I just assumed I'd missunderstood since this was an FPGA group. I'd concur with the other posters - microprocessor is the way to go. I'd recommend a download of their parts selector software (free) and have a browse. FPGA's require far too much work for everyday tasks such as this. -- john ========================= http://johntech.co.uk =========================
Reply by ●March 30, 20192019-03-30
Den 2019-03-30 kl. 11:00, skrev john:> In article <q7nbpc$1v9l$1@gioia.aioe.org>, aprichelieu@gmail.com says... >> >> Once you have programmed the microcontroller, you use a write pin to >> program the part, and a read pin to read out the part. >> These things can be connected to DMA, for quite high speed. >> Since the reads were "slow", I bet this is good enough. >> Piece of cake. >> >> The build to add an additional memory array of 128 bytes takes a >> fraction of a second. It is not complex. It is well known technology. >> To say that this is not straightforward shows that you know little about >> MCUs. >> >> AP >> > > The first thing that went through my mind when I saw the original post > was "microchip PIC" - the size of a full stop. > I just assumed I'd missunderstood since this was an FPGA group. > > I'd concur with the other posters - microprocessor is the way to go. > I'd recommend a download of their parts selector software (free) and have a > browse. > FPGA's require far too much work for everyday tasks such as this. >The Event System originally implemented in the AVR is probably quite useful for this application. It is available in some Cortex-M parts as well where the NMI can be used for almost no delay response. AP
Reply by ●April 2, 20192019-04-02
Am Donnerstag, 28. März 2019 13:43:07 UTC+1 schrieb Stef:> We have a product that includes a small parallel OTP memory. These devices > get very hard to get and no easy alternative is available that fits in the > very small available space. A PLCC32 EPROM will not fit unfortunately. > Since the memory array is small (256x4 bits), I was thinking this could > easily fit into a CPLD or FPGA. But how to program this?[..]> A device like the Lattice ispMACH 4000 seems a possible candidate.Many FPGAs require an external EEPROM for storing the Bitfile. All those will be no choice for you. Whats left is in fact some old CPLDs, Lattice and Microsemi which all use internal Flash. The CPLDs would be in many occasions too small to store 1024 bits random content. I understand it is something like 256 times 4 bit. This means you have 8 bit address for 4 bit result. A function calculating 4 bits result from 8 bit address can be either very simple (eg: Bit0=not Adress(0), bit1=Address(0), bit2=address(1) xor address(2), bit3 = address(3) and address(4)) or very complex (example left to you). Due to Fan-In/Fan-Out constraints a function looking simple can simple explode in size, my experience says you cannot say on first glance how easy or complex a table transfers into a combinatorical circuit. So the question if you have 10 different tables which of those require what size of combinatoric is hard to answer before implementing it. On the other hand most FPGAs packages might be too large in size for your board design, if a simple EEPROM is allready too large. No idea what cou can accept. You might want to check out the Microsemi ProAsic3 technology which provides an 1k EEPROM for user access. The smallest package would be the A3PN010 in QN48 (6x6 mm) regards Thomas
Reply by ●April 3, 20192019-04-03
On Tuesday, April 2, 2019 at 7:19:09 AM UTC-4, Thomas Stanka wrote:> Am Donnerstag, 28. M=C3=A4rz 2019 13:43:07 UTC+1 schrieb Stef: > > We have a product that includes a small parallel OTP memory. These devi=ces> > get very hard to get and no easy alternative is available that fits in =the> > very small available space. A PLCC32 EPROM will not fit unfortunately. > > Since the memory array is small (256x4 bits), I was thinking this could > > easily fit into a CPLD or FPGA. But how to program this? > [..] > > A device like the Lattice ispMACH 4000 seems a possible candidate. >=20 > Many FPGAs require an external EEPROM for storing the Bitfile. All those =will be no choice for you.>=20 > Whats left is in fact some old CPLDs, Lattice and Microsemi which all use=internal Flash. The CPLDs would be in many occasions too small to store 10= 24 bits random content.=20>=20 > I understand it is something like 256 times 4 bit. This means you have 8 =bit address for 4 bit result.=20> A function calculating 4 bits result from 8 bit address can be either ver=y simple (eg: Bit0=3Dnot Adress(0), bit1=3DAddress(0), bit2=3Daddress(1) xo= r address(2), bit3 =3D address(3) and address(4)) or very complex (example = left to you).>=20 > Due to Fan-In/Fan-Out constraints a function looking simple can simple ex=plode in size, my experience says you cannot say on first glance how easy o= r complex a table transfers into a combinatorical circuit.> So the question if you have 10 different tables which of those require wh=at size of combinatoric is hard to answer before implementing it.>=20 > On the other hand most FPGAs packages might be too large in size for your=board design, if a simple EEPROM is allready too large. No idea what cou c= an accept.>=20 > You might want to check out the Microsemi ProAsic3 technology which provi=des an 1k EEPROM for user access. The smallest package would be the A3PN010= in QN48 (6x6 mm)>=20 > regards ThomasYou seem to have not read most of the posts in this thread. There have bee= n specific FPGAs mentioned which will do the job the OP needs. He seems to= prefer an MCU approach because he is more familiar with MCUs than FPGAs. = =20 --=20 Rick C. -+- Get a 1,000 miles of free Supercharging -+- Tesla referral code - https://ts.la/richard11209
Reply by ●April 4, 20192019-04-04
On 2019-04-03 gnuarm.deletethisbit@gmail.com wrote in comp.arch.fpga:> On Tuesday, April 2, 2019 at 7:19:09 AM UTC-4, Thomas Stanka wrote: >> >> Many FPGAs require an external EEPROM for storing the Bitfile. All those will be no choice for you.A dual package solution is not prefered, but if the packages are small enough, it might fit. Double sided placement could be a last resort as long as the bottom components are <= 1mm high.>> >> On the other hand most FPGAs packages might be too large in size for your board design, if a simple EEPROM is allready too large. No idea what cou can accept.A TSOP EEPROM would be a good mechanical fit, but unfortunately it is electrically unsuitable as you need access to all address and data pins for programming. I managed to get an SOIC28 (17.9 x 10.3 mm) on the board after reducing some clearances and pad sizes, but that relies on the connector and memory pins 'interleaving' a little (pitch 2.54 and 1.27 mm). So generically I would say the maximum size is 18 x 9 mm>> You might want to check out the Microsemi ProAsic3 technology which provides an 1k EEPROM for user access. The smallest package would be the A3PN010 in QN48 (6x6 mm)That would fit mechanically.> You seem to have not read most of the posts in this thread. There have been specific FPGAs mentioned which will do the job the OP needs. He seems to prefer an MCU approach because he is more familiar with MCUs than FPGAs.It is not that I prefer an MCU approach, but I am indeed more comfortable with MCU's. And if I go that way and need help, I think it's best not to ask in an FPGA group. ;-) There are other issues against the MCU approach. One of them is that it may (this is not sure) be harder for certification than a CPLD solution. For now I am still trying to find all possible solutions (and still hoping for a suitable memory device to pop up :-( ) so I can come up with a good overview of solutions. The overview should include all costs and effort for components, development, tools, certification, in-line programming, etc. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Every man takes the limits of his own field of vision for the limits of the world. -- Schopenhauer
