hello, i need to solve this problem in verilog:Up/Down Binary Counter with Dynamic Count-to Flag this is start cod: module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn, inst_load, inst_cen, inst_clk, inst_reset, count_inst, tercnt_inst ); parameter width = 8; input [width-1 : 0] inst_data; input [width-1 : 0] inst_count_to; input inst_up_dn; input inst_load; input inst_cen; input inst_clk; input inst_reset; output [width-1 : 0] count_inst; output tercnt_inst; // Instance of DW03_bictr_dcnto DW03_bictr_dcnto #(width) U1 ( .data(inst_data), .count_to(inst_count_to), .up_dn(inst_up_dn), .load(inst_load), .cen(inst_cen), .clk(inst_clk), .reset(inst_reset), .count(count_inst), .tercnt(tercnt_inst) ); endmodule i already have: test.v module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn, inst_load, inst_cen, inst_clk, inst_reset, count_inst, tercnt_inst ); parameter width = 8; input [width-1 : 0] inst_data; input [width-1 : 0] inst_count_to; input inst_up_dn; input inst_load; input inst_cen; input inst_clk; input inst_reset; output [width-1 : 0] count_inst; output tercnt_inst; // Instance of DW03_bictr_dcnto always @(posedge inst_clk or negedge inst_reset) if (~inst_reset) begin count_inst<={width{4'b0000}}; end else begin if(~inst_load) begin count_inst<=inst_data; end else begin if (inst_cen) begin if (inst_up_dn) begin count_inst<=count_inst+1; if (count_inst==inst_count_to) tercnt_inst<=1; end else begin count_inst<=count_inst-1; if (count_inst==inst_count_to) tercnt_inst<=1; end end end end always @(count_inst or inst_up_dn) if (&count_inst && inst_up_dn) tercnt_inst <= 1; else if (~|count_inst && !inst_up_dn) tercnt_inst <= 1; else tercnt_inst <= 0; DW03_bictr_dcnto #(width) U1 ( .data(inst_data), .count_to(inst_count_to), .inst_up_dn(inst_up_dn), .load(inst_load), .cen(inst_cen), .clk(inst_clk), .reset(inst_reset), .count(count_inst), .tercnt(tercnt_inst) ); endmodule I need the test_branch.V and DUT.V Thanks a lot!
Up/Down Binary Counter with Dynamic Count-to Flag
Started by ●April 21, 2019
Reply by ●April 22, 20192019-04-22
On Sunday, April 21, 2019 at 6:39:17 PM UTC-4, buse.vic...@decathlon.com wrote:> hello, i need to solve this problem in verilog:Up/Down Binary Counter with Dynamic Count-to Flag > > this is start cod: > > > module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn, > inst_load, inst_cen, inst_clk, inst_reset, count_inst, tercnt_inst ); > parameter width = 8; > input [width-1 : 0] inst_data; > input [width-1 : 0] inst_count_to; > input inst_up_dn; > input inst_load; > input inst_cen; > input inst_clk; > input inst_reset; > output [width-1 : 0] count_inst; > output tercnt_inst; > // Instance of DW03_bictr_dcnto > DW03_bictr_dcnto #(width) > U1 ( .data(inst_data), .count_to(inst_count_to), .up_dn(inst_up_dn), > .load(inst_load), .cen(inst_cen), .clk(inst_clk), > .reset(inst_reset), .count(count_inst), .tercnt(tercnt_inst) ); > endmodule > > > i already have: test.v > > module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn, > inst_load, inst_cen, inst_clk, inst_reset, count_inst, tercnt_inst ); > parameter width = 8; > input [width-1 : 0] inst_data; > input [width-1 : 0] inst_count_to; > input inst_up_dn; > input inst_load; > input inst_cen; > input inst_clk; > input inst_reset; > output [width-1 : 0] count_inst; > output tercnt_inst; > // Instance of DW03_bictr_dcnto > always @(posedge inst_clk or negedge inst_reset) > if (~inst_reset) begin > count_inst<={width{4'b0000}}; > end > else begin > if(~inst_load) begin > count_inst<=inst_data; > end > else begin > if (inst_cen) begin > if (inst_up_dn) begin > count_inst<=count_inst+1; > if (count_inst==inst_count_to) > tercnt_inst<=1; > end > else begin > count_inst<=count_inst-1; > if (count_inst==inst_count_to) > tercnt_inst<=1; > end > end > end > end > always @(count_inst or inst_up_dn) > if (&count_inst && inst_up_dn) > tercnt_inst <= 1; > else > if (~|count_inst && !inst_up_dn) > tercnt_inst <= 1; > else > tercnt_inst <= 0; > > DW03_bictr_dcnto #(width) > U1 ( .data(inst_data), .count_to(inst_count_to), .inst_up_dn(inst_up_dn), > .load(inst_load), .cen(inst_cen), .clk(inst_clk), > .reset(inst_reset), .count(count_inst), .tercnt(tercnt_inst) ); > endmodule > > > I need the test_branch.V and DUT.V > Thanks a lot!You are welcome. :) -- Rick C. - Get a 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
Reply by ●April 22, 20192019-04-22
On 22/04/2019 00:39, buse.victorstefan@decathlon.com wrote:> hello, i need to solve this problem in verilog:Up/Down Binary Counter with Dynamic Count-to FlagOoooh that's a tough one. Your teacher is terribly mean. No, seriously, do your homework yourself. We'll gladly help but nobody here will do it for you. Nicolas