Assume I'm a pointy-haired boss trying to help one of my guys. I think that... The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It figures out what the boot device is (serial flash, SD card, whatever) and reads in a secondary boot program, which the Xilinx tools provide as part of a build. That loader then reads the entire FPGA config bitstream into DRAM, and sets up a giant DMA transfer to configure the FPGA. That's all standard in the tools. But what if there's no DRAM? My guy thinks he will have to write his own ARM application, which is booted at load time, and inside that would be a routine to read from the boot media and configure the FPGA in chunks, using a small uP RAM buffer, maybe DMA or maybe not. He figures he could do that in a few days. Seems to me that Xilinx should support booting up a ZYNQ without DRAM. Does the tool chain support that (people here think not) or is there some loader already coded somewhere? (Our support, through a distributor, isn't very good.) Thanks -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
bare-metal ZYNQ
Started by ●June 12, 2019
Reply by ●June 12, 20192019-06-12
Am 13.06.19 um 01:32 schrieb John Larkin:> > > Assume I'm a pointy-haired boss trying to help one of my guys. > > I think that... > > The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It > figures out what the boot device is (serial flash, SD card, whatever) > and reads in a secondary boot program, which the Xilinx tools provide > as part of a build. That loader then reads the entire FPGA config > bitstream into DRAM, and sets up a giant DMA transfer to configure the > FPGA. That's all standard in the tools. > > But what if there's no DRAM? My guy thinks he will have to write his > own ARM application, which is booted at load time, and inside that > would be a routine to read from the boot media and configure the FPGA > in chunks, using a small uP RAM buffer, maybe DMA or maybe not. He > figures he could do that in a few days. > > Seems to me that Xilinx should support booting up a ZYNQ without DRAM. > Does the tool chain support that (people here think not) or is there > some loader already coded somewhere?A Zynq without RAM is like a car without tyres. Maybe you can peek in the sources for the Red Pitaya; it is also based on a Zynq and there are a number of Linuxes available for it. I have one, but have avoided digging that deep. If the loading interface is only remotely similar to other Xilinx FPGAs, it should be easy to replace the one large DMA xfer by many small ones. regards, Gerhard
Reply by ●June 12, 20192019-06-12
On Thu, 13 Jun 2019 02:07:55 +0200, Gerhard Hoffmann <dk4xp@arcor.de> wrote:>Am 13.06.19 um 01:32 schrieb John Larkin: >> >> >> Assume I'm a pointy-haired boss trying to help one of my guys. >> >> I think that... >> >> The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It >> figures out what the boot device is (serial flash, SD card, whatever) >> and reads in a secondary boot program, which the Xilinx tools provide >> as part of a build. That loader then reads the entire FPGA config >> bitstream into DRAM, and sets up a giant DMA transfer to configure the >> FPGA. That's all standard in the tools. >> >> But what if there's no DRAM? My guy thinks he will have to write his >> own ARM application, which is booted at load time, and inside that >> would be a routine to read from the boot media and configure the FPGA >> in chunks, using a small uP RAM buffer, maybe DMA or maybe not. He >> figures he could do that in a few days. >> >> Seems to me that Xilinx should support booting up a ZYNQ without DRAM. >> Does the tool chain support that (people here think not) or is there >> some loader already coded somewhere? > >A Zynq without RAM is like a car without tyres.There's enough of sram internal to the chip for many applications.> >Maybe you can peek in the sources for the Red Pitaya; it is also >based on a Zynq and there are a number of Linuxes available >for it. I have one, but have avoided digging that deep. > >If the loading interface is only remotely similar to other >Xilinx FPGAs, it should be easy to replace the one large DMA >xfer by many small ones.Yes, but I was thinking that someone has already done the work. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Reply by ●June 13, 20192019-06-13
On a sunny day (Wed, 12 Jun 2019 16:32:35 -0700) it happened John Larkin <jjlarkin@highland_snip_technology.com> wrote in <qm13gel4ifba24lb4p8gdeeusufc2b433b@4ax.com>:>But what if there's no DRAM?That thing runs Linux? Does not Linux use the DRAM? If not using Linux and DRAM then a simpler cheaper FPGA board?
Reply by ●June 13, 20192019-06-13
On 13/06/19 01:35, John Larkin wrote:> On Thu, 13 Jun 2019 02:07:55 +0200, Gerhard Hoffmann <dk4xp@arcor.de> > wrote: > >> Am 13.06.19 um 01:32 schrieb John Larkin: >>> >>> >>> Assume I'm a pointy-haired boss trying to help one of my guys. >>> >>> I think that... >>> >>> The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It >>> figures out what the boot device is (serial flash, SD card, whatever) >>> and reads in a secondary boot program, which the Xilinx tools provide >>> as part of a build. That loader then reads the entire FPGA config >>> bitstream into DRAM, and sets up a giant DMA transfer to configure the >>> FPGA. That's all standard in the tools. >>> >>> But what if there's no DRAM? My guy thinks he will have to write his >>> own ARM application, which is booted at load time, and inside that >>> would be a routine to read from the boot media and configure the FPGA >>> in chunks, using a small uP RAM buffer, maybe DMA or maybe not. He >>> figures he could do that in a few days. >>> >>> Seems to me that Xilinx should support booting up a ZYNQ without DRAM. >>> Does the tool chain support that (people here think not) or is there >>> some loader already coded somewhere? >> >> A Zynq without RAM is like a car without tyres. > > There's enough of sram internal to the chip for many applications.For small software applications, it might be worth considering using the same FPGA fabric (Artix 7 or Kintex 7) and using a softcore processor. That would sidestep those problems, might be cheaper, and would bring its own, hopefully lesser, problems.
Reply by ●June 13, 20192019-06-13
On Wed, 12 Jun 2019 16:32:35 -0700, John Larkin wrote:> Assume I'm a pointy-haired boss trying to help one of my guys. > > I think that... > > The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It figures > out what the boot device is (serial flash, SD card, whatever) and reads > in a secondary boot program, which the Xilinx tools provide as part of a > build. That loader then reads the entire FPGA config bitstream into > DRAM, and sets up a giant DMA transfer to configure the FPGA. That's all > standard in the tools. > > But what if there's no DRAM? My guy thinks he will have to write his own > ARM application, which is booted at load time, and inside that would be > a routine to read from the boot media and configure the FPGA in chunks, > using a small uP RAM buffer, maybe DMA or maybe not. He figures he could > do that in a few days. > > Seems to me that Xilinx should support booting up a ZYNQ without DRAM. > Does the tool chain support that (people here think not) or is there > some loader already coded somewhere? > > (Our support, through a distributor, isn't very good.) > > ThanksOur Zynq 7 boards have DRAM (natch) but we choose to load the PL (FPGA fabric) after boot rather than as part of the FSBL. What you want to do is possible, but you won't get much support from Xilinx. You will also lose some of the built-in security features. Considering the costs of DRAM (plus the extra PCB layers you will need) you might be better off putting it on the board. I'm assuming you don't have really large volumes, of course. Allan
Reply by ●June 13, 20192019-06-13
On Thu, 13 Jun 2019 08:06:05 +0100, Tom Gardner <spamjunk@blueyonder.co.uk> wrote:>On 13/06/19 01:35, John Larkin wrote: >> On Thu, 13 Jun 2019 02:07:55 +0200, Gerhard Hoffmann <dk4xp@arcor.de> >> wrote: >> >>> Am 13.06.19 um 01:32 schrieb John Larkin: >>>> >>>> >>>> Assume I'm a pointy-haired boss trying to help one of my guys. >>>> >>>> I think that... >>>> >>>> The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It >>>> figures out what the boot device is (serial flash, SD card, whatever) >>>> and reads in a secondary boot program, which the Xilinx tools provide >>>> as part of a build. That loader then reads the entire FPGA config >>>> bitstream into DRAM, and sets up a giant DMA transfer to configure the >>>> FPGA. That's all standard in the tools. >>>> >>>> But what if there's no DRAM? My guy thinks he will have to write his >>>> own ARM application, which is booted at load time, and inside that >>>> would be a routine to read from the boot media and configure the FPGA >>>> in chunks, using a small uP RAM buffer, maybe DMA or maybe not. He >>>> figures he could do that in a few days. >>>> >>>> Seems to me that Xilinx should support booting up a ZYNQ without DRAM. >>>> Does the tool chain support that (people here think not) or is there >>>> some loader already coded somewhere? >>> >>> A Zynq without RAM is like a car without tyres. >> >> There's enough of sram internal to the chip for many applications. > >For small software applications, it might be worth >considering using the same FPGA fabric (Artix 7 or >Kintex 7) and using a softcore processor. > >That would sidestep those problems, might be cheaper, >and would bring its own, hopefully lesser, problems.That has been suggested. There are downsides: New tool chain Slower CPU, but that seldom matters here Uses valuable FPGA resources, especially RAM Floating point would use more The Zynq ARM comes with all sorts of hard goodies, FP, counter/timers, SPI, UARTS, DMA, I2C, like that, all built. The downside of the ZYNQ is that some balls are dedicated to uP and some to FPGA. Pity they didn't allow dual use on them. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●June 13, 20192019-06-13
On Thu, 13 Jun 2019 06:14:09 GMT, Jan Panteltje <pNaOnStPeAlMtje@yahoo.com> wrote:>On a sunny day (Wed, 12 Jun 2019 16:32:35 -0700) it happened John Larkin ><jjlarkin@highland_snip_technology.com> wrote in ><qm13gel4ifba24lb4p8gdeeusufc2b433b@4ax.com>: > >>But what if there's no DRAM? > > >That thing runs Linux? >Does not Linux use the DRAM? > > >If not using Linux and DRAM then a simpler cheaper FPGA board?I said "bare metal." Separate FPGA and CPU chips is an option that we use a lot already, but it needs a chip-chip parallel interface that uses a lot of balls, or a slow SPI link. The NXP uP that we usually use for this combo, LPC3250, looks to be EOL, so we're looking for a next-generation product platform. -- John Larkin Highland Technology, Inc lunatic fringe electronics
Reply by ●June 13, 20192019-06-13
On 13/06/2019 17:09, John Larkin wrote:> On Thu, 13 Jun 2019 06:14:09 GMT, Jan Panteltje > <pNaOnStPeAlMtje@yahoo.com> wrote: > >> On a sunny day (Wed, 12 Jun 2019 16:32:35 -0700) it happened John Larkin >> <jjlarkin@highland_snip_technology.com> wrote in >> <qm13gel4ifba24lb4p8gdeeusufc2b433b@4ax.com>: >> >>> But what if there's no DRAM? >> >> >> That thing runs Linux? >> Does not Linux use the DRAM? >> >> >> If not using Linux and DRAM then a simpler cheaper FPGA board? > > I said "bare metal." > > Separate FPGA and CPU chips is an option that we use a lot already, > but it needs a chip-chip parallel interface that uses a lot of balls, > or a slow SPI link. > > The NXP uP that we usually use for this combo, LPC3250, looks to be > EOL, so we're looking for a next-generation product platform. >Consider NXP's i.mx RT family. They have Cortex-M7 cpus at about 600 MHz, and have quad SPI or octal SPI links. These are typically for flash for booting, but you could use one link for the flash and one for a high speed interface to the FPGA.
Reply by ●June 13, 20192019-06-13
On 13/06/2019 16:09, John Larkin wrote:> On Thu, 13 Jun 2019 06:14:09 GMT, Jan Panteltje > <pNaOnStPeAlMtje@yahoo.com> wrote: > >> On a sunny day (Wed, 12 Jun 2019 16:32:35 -0700) it happened John Larkin >> <jjlarkin@highland_snip_technology.com> wrote in >> <qm13gel4ifba24lb4p8gdeeusufc2b433b@4ax.com>: >> >>> But what if there's no DRAM? >> >> >> That thing runs Linux? >> Does not Linux use the DRAM? >> >> >> If not using Linux and DRAM then a simpler cheaper FPGA board? > > I said "bare metal." > > Separate FPGA and CPU chips is an option that we use a lot already, > but it needs a chip-chip parallel interface that uses a lot of balls, > or a slow SPI link. > > The NXP uP that we usually use for this combo, LPC3250, looks to be > EOL, so we're looking for a next-generation product platform. > >May not be relevant right now but you could look at the ST M-7s as a step beyond the NXP part. STM32H7... 400Mhz, lots of RAM and flash on chip 64 bit FPU, and multi bit SPI ("dual quad SPI" in ST speak) which would ease that uP<->FPGA bottleneck a bit. They claim max 133 MHz clock on it so with 8 bit data that's quite quick. The downside is that the FPGA will need to pretend it's a flash memory but that may not be too hard. MK --- This email has been checked for viruses by AVG. https://www.avg.com
