Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution

Well, I'm not sure if anyone here has had the same problem, but I have, 
and it has been driving me nuts.  My primary machine is a laptop, which 
has no parallel port, so I am stuck with USB.  Also, I am in a class 
where we are doing projects using the Spartan-3 Starter Kit from Digilent.

Since I have no parallel port, I have been using Digilent's JTAG-USB 
cable, which, for the most part, works great.  However, there are two 
problems.

1. You cannot use Xilinx IMPACT to program the Spartan-3
2. The external SRAM does not work when using a .bit file

Well, #2 seems awfully strange.  I know it did for me, I thought I was 
having a problem with VHDL, and that's why I thought it wasn't working. 
  Well, I spent a long time tinkering with it over our winter break (I 
know, I know, but it's what I did) and just today I came up with the 
solution.

A little explanation for this is probably needed.  Basically, anything I 
write and compile in IMPACT would work fine.  LEDs light up, the 
7-segment display works fine, everything I've done works great. 
However, every time I tried to write to the SRAM, nothing changed, I 
simply got back garbage/random data.  Every time, no questions asked, it 
just didn't work.  To make a long story short, here's a solution I 
discovered (which, is a whole another story to how I figured it out).

1. Start IMPACT
2. Edit -> Add Device -> Xilinx Device
3. Loaded c:\Program Files\Xilinx\spartan3\data\xc3s200_ft256.bsd
4. Right-Clicked Device, Assigned Configuration File
5. Mode -> File Mode
6. Clicked SVF-STAPL-XSVF tab, clicked "Yes" when it asked to load from 
Boundary Scan
7. Chose to generate a new SVF file, named it
8. Right-Clicked Device, chose Program.
9. Output -> SVF -> Stop Writing to SVF File
10. Quit Impact
11. Started Export, did Device Scan, loaded SVF into the xc3s200, set 
the prom to bypass, hit program.  Everything worked right.

Seems like a strange solution, but what I want to know, has anyone here 
had a problem like this?  I have a feeling that loading a different .BSD 
file for other Xilinx chips should work just as well with the JTAG-USB 
cable/Digilent's ExPort software, but I couldn't tell you.

Hope this helps people out.

If anyone wants to contact me with any more information via email, 
please use: skroll at gmail dot com

I don't know about your particular problem, but with regard to the
parallel port, you can buy a PCMCIA to Parallel port converter.
http://www.quatech.com/catalog/parallel_pcmcia.php
They should work for any FPGA board that needs parallel port since the
converter works at lower hardware level and it fools the operating
system to think that it really has a parallel port. From the device
manager, it would appear that you really have a native parallel port.
If you buy it , make sure you got rev. F or later. It fixed
incompatibility problem with some newer laptop. If you have the earlier
rev, contact them for the RMA and they will exchange it for you.

Hendra

#1 there is no way (til today) to create impact compatible 3rd party
programmers other than those that are cable III compliant, (unless usb
platform cable is integrated fully in the design) - hence the digilent
cable is not supported by impact

#2 this what I dont understand - FPGA and all connected stuff (SRAM
whatever) will work same way no matter what means are used to configure
the FPGA given the FPGA is really configured properly. So configuring
the FPGA with .bit file using impact or SVF file and some 3rd party
tool, should get the FGPA into same working condition.

If you had some trouble then its must some trick bug of the digilient
export software I guess

btw jtag config is a bit tricky, namly it is possible have DONE=1 when
FPGA is not configured at all etc..

Antti

Antti wrote:
> btw jtag config is a bit tricky, namly it is possible have DONE=1 when
> FPGA is not configured at all etc..

One thing that I frequently see in some Xilinx FPGA boards is when you
got an error like Done is not high or something like that, you should
unplug the power cable, replug it and reprogram the board. If it still
doesn't work, unplug the parallel cable or whatever connection you have
as well.

Hendra

Scott M. Kroll wrote:
>
> 2. The external SRAM does not work when using a .bit file
>
 Could you clarify exactly what you mean here; are you
using the Digilent JTAG utility to program the on-board prom,
or to directly configure the FPGA via JTAG?

 One thing I've seen with IMPACT generated SVF files on both
V2P's and the S3 starter kit, is the need for one last JTAG
operation to "wake up" the part.

  IIRC, in the Digilent tool, after loading the FPGA with the
config PROM in BYPASS, just try a device id on the config
PROM and see if that fixes it.

  Also, I think I've had to change the JP1 bitstream readback
jumper setting to "disable" to get consistent results for JTAG
download; you may also want to change the configuration mode
jumpers to "JTAG"

  If the DCM doesn't start up after re-configuration, your static
logic would work but any DCM clocked logic would not:
 Answer Record 11778:
    "Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures
     correctly after PROG is pulsed, but DLL/DCM/DCI does
     not function correctly when reconfigured"

 Similar things can happen if the part almost, but not quite, finishes
configuration and ends up in a configured state with GSR or GTS
still asserted.

 To help sort out what is happening, create a test design with:
   - an LED driven from a switch input (no registers)
   - a blinky LED counter driven from the input clock WITHOUT a DCM
   - a blinky LED counter driven from a DCM sourced clock
   - LED's on DCM LOCKED and "clock stopped" status bit

Brian

Brian Davis wrote:
> Scott M. Kroll wrote:
>> 2. The external SRAM does not work when using a .bit file
>>
>  Could you clarify exactly what you mean here; are you
> using the Digilent JTAG utility to program the on-board prom,
> or to directly configure the FPGA via JTAG?
> 
>  One thing I've seen with IMPACT generated SVF files on both
> V2P's and the S3 starter kit, is the need for one last JTAG
> operation to "wake up" the part.
> 
>   IIRC, in the Digilent tool, after loading the FPGA with the
> config PROM in BYPASS, just try a device id on the config
> PROM and see if that fixes it.
> 
>   Also, I think I've had to change the JP1 bitstream readback
> jumper setting to "disable" to get consistent results for JTAG
> download; you may also want to change the configuration mode
> jumpers to "JTAG"
> 
>   If the DCM doesn't start up after re-configuration, your static
> logic would work but any DCM clocked logic would not:
>  Answer Record 11778:
>     "Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures
>      correctly after PROG is pulsed, but DLL/DCM/DCI does
>      not function correctly when reconfigured"
> 
>  Similar things can happen if the part almost, but not quite, finishes
> configuration and ends up in a configured state with GSR or GTS
> still asserted.
> 
>  To help sort out what is happening, create a test design with:
>    - an LED driven from a switch input (no registers)
>    - a blinky LED counter driven from the input clock WITHOUT a DCM
>    - a blinky LED counter driven from a DCM sourced clock
>    - LED's on DCM LOCKED and "clock stopped" status bit
> 
> Brian
> 

It's very strange, but here's what I meant: I am using Digilent's JTAG 
utility (it's called Export) to program the FPGA via JTAG.  Using IMPACT 
to create the .bit file, and then program the FPGA with the .bit. 
Digilent's Export tool only supports .bit and .svf files.  If I program 
the FPGA via the .bit file, the SRAM never writes, and feeds back random 
garbage, never writes correctly.  Some ramtesting vhdl I found for the 
Spartan-3 Starter doesn't work, nor does anything I've written.  It 
constantly reads back garbage data.  When I go into IMPACT, and generate 
a SVF of the chip programming (with the same .bit file, no less), and 
then load that into Digilent's tool, the SRAM works correctly (reads 
back fine, the ram tester comes out ok).

I know it seems bizarre, but it's what happens.

Scott M. Kroll wrote:
>
> It's very strange, but here's what I meant: I am using Digilent's JTAG
> utility (it's called Export) to program the FPGA via JTAG.  Using IMPACT
> to create the .bit file, and then program the FPGA with the .bit.
> Digilent's Export tool only supports .bit and .svf files.  If I program
> the FPGA via the .bit file, the SRAM never writes, and feeds back random
> garbage, never writes correctly.

 OK, I'll try that tonight and see what I see.

 BTW, what versions of ISE and Export are you using ?

>  Some ramtesting vhdl I found for the  Spartan-3 Starter doesn't work,
> nor does anything I've written.

 Follow the bouncing links for my S3 kit SRAM test code and notes:
   http://groups.google.com/group/comp.arch.fpga/msg/ee222450bf8e47c8

 If I ever find time to debug the S3 -ES DCM oddities I've been seeing,
I'll post a new version of that code that runs the S3 starter kit SRAM
(pipelined) at around 60 MHz.

Brian

Scott M. Kroll wrote:

> It's very strange, but here's what I meant: I am using Digilent's JTAG
> utility (it's called Export) to program the FPGA via JTAG.  Using IMPACT
> to create the .bit file, and then program the FPGA with the .bit.
> Digilent's Export tool only supports .bit and .svf files.  If I program
> the FPGA via the .bit file, the SRAM never writes, and feeds back random
> garbage, never writes correctly.

Okay, let me see if I understand this correctly - the digilent
programmer does not seem to be able to make a .bit file work, but if
you use the xilinx tool to turn .bit into .svf, the digilent programmer
can load that.

Your only evidence of working/not working to date is the ram test.  But
it's probably that the programming more generally fails?

Anyway, my impression is that a .bit file is just data, while a .svf
file is data expanded into explicit instructions for how to wiggle the
jtag lines to program it into a xilinx part - all the thinking is
already done, only the execution remains.  This suggests that your
problem is that the digilent programmer is not using (is not configured
to use) the right programming algorithm for the part in question.  When
it's mindlessly executing the .svf instructions things work, when it's
taking responsibility for figuring out how to program a .bit, it fails.

You could either take that up with digilent, or if you want to
streamline your intermediate step, the xilinx tools can be run
command-line style from scripts to do your translation.

On Wed, 08 Mar 2006 07:54:36 -0500, "Scott M. Kroll" <none@nowhere.com> wrote:

>Brian Davis wrote:
>> Scott M. Kroll wrote:
>>> 2. The external SRAM does not work when using a .bit file
>>>
>>  Could you clarify exactly what you mean here; are you
>> using the Digilent JTAG utility to program the on-board prom,
>> or to directly configure the FPGA via JTAG?
>> 
>>  One thing I've seen with IMPACT generated SVF files on both
>> V2P's and the S3 starter kit, is the need for one last JTAG
>> operation to "wake up" the part.
>> 
>>   IIRC, in the Digilent tool, after loading the FPGA with the
>> config PROM in BYPASS, just try a device id on the config
>> PROM and see if that fixes it.
>> 
>>   Also, I think I've had to change the JP1 bitstream readback
>> jumper setting to "disable" to get consistent results for JTAG
>> download; you may also want to change the configuration mode
>> jumpers to "JTAG"
>> 
>>   If the DCM doesn't start up after re-configuration, your static
>> logic would work but any DCM clocked logic would not:
>>  Answer Record 11778:
>>     "Virtex/-E/-II/-II Pro, Spartan-II/-IIE/-3 - Device configures
>>      correctly after PROG is pulsed, but DLL/DCM/DCI does
>>      not function correctly when reconfigured"
>> 
>>  Similar things can happen if the part almost, but not quite, finishes
>> configuration and ends up in a configured state with GSR or GTS
>> still asserted.
>> 
>>  To help sort out what is happening, create a test design with:
>>    - an LED driven from a switch input (no registers)
>>    - a blinky LED counter driven from the input clock WITHOUT a DCM
>>    - a blinky LED counter driven from a DCM sourced clock
>>    - LED's on DCM LOCKED and "clock stopped" status bit
>> 
>> Brian
>> 
>
>It's very strange, but here's what I meant: I am using Digilent's JTAG 
>utility (it's called Export) to program the FPGA via JTAG.  Using IMPACT 
>to create the .bit file, and then program the FPGA with the .bit. 
>Digilent's Export tool only supports .bit and .svf files.  If I program 
>the FPGA via the .bit file, the SRAM never writes, and feeds back random 
>garbage, never writes correctly.  Some ramtesting vhdl I found for the 
>Spartan-3 Starter doesn't work, nor does anything I've written.  It 
>constantly reads back garbage data.  When I go into IMPACT, and generate 
>a SVF of the chip programming (with the same .bit file, no less), and 
>then load that into Digilent's tool, the SRAM works correctly (reads 
>back fine, the ram tester comes out ok).
>
>I know it seems bizarre, but it's what happens.

A quick "reality check" on programming problems is to program the file into the flash. 
If it behaves differently then it's definitely a download problem

Believe it or not, every other component seems to work.  I wrote a
working UART and was able to send data to and from a terminal no
problem, as well as all the LEDs and Switches work.  I've been talking
to Digilent, and they have been working with me in trying to figure out
what's causing it.  Only thing that doesn't seem to work is the SRAM
when programming via a .bit file.  Everything else is fine, which is
why I hadn't noticed a problem until I tried to use the SRAM.


cs_posting@hotmail.com wrote:
> Scott M. Kroll wrote:
>
> > It's very strange, but here's what I meant: I am using Digilent's JTAG
> > utility (it's called Export) to program the FPGA via JTAG.  Using IMPACT
> > to create the .bit file, and then program the FPGA with the .bit.
> > Digilent's Export tool only supports .bit and .svf files.  If I program
> > the FPGA via the .bit file, the SRAM never writes, and feeds back random
> > garbage, never writes correctly.
>
> Okay, let me see if I understand this correctly - the digilent
> programmer does not seem to be able to make a .bit file work, but if
> you use the xilinx tool to turn .bit into .svf, the digilent programmer
> can load that.
>
> Your only evidence of working/not working to date is the ram test.  But
> it's probably that the programming more generally fails?
>
> Anyway, my impression is that a .bit file is just data, while a .svf
> file is data expanded into explicit instructions for how to wiggle the
> jtag lines to program it into a xilinx part - all the thinking is
> already done, only the execution remains.  This suggests that your
> problem is that the digilent programmer is not using (is not configured
> to use) the right programming algorithm for the part in question.  When
> it's mindlessly executing the .svf instructions things work, when it's
> taking responsibility for figuring out how to program a .bit, it fails.
>
> You could either take that up with digilent, or if you want to
> streamline your intermediate step, the xilinx tools can be run
> command-line style from scripts to do your translation.