LEON processor core

Started by Martin Schoeberl March 12, 2006
I'm wondering why there are so few messages about LEON [1]
in this group. LEON looks like a very solid design (used
by the ESA) and it is available in a GPL version.
Could be a vendor independent replacement of NIOS/MicroBlaze
with a path to an ASIC.
The configuration is done via a simple Tcl/Tk script and
the Makefile contains several targets. Works out-of-the-box
for available tragets. Adaption to a new FPGA board [2] took
me a few (some) hours - not so bad.

What's your experience?

Martin


[1]
http://www.gaisler.com/cms4_5_3/index.php?option=com_content&task=view&id=13&Itemid=53

[2] http://www.jopdesign.com/nios.jsp 


"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag 
news:441451f8$0$11610$3b214f66@tunews.univie.ac.at...
> I'm wondering why there are so few messages about LEON [1] > in this group. LEON looks like a very solid design (used > by the ESA) and it is available in a GPL version. > Could be a vendor independent replacement of NIOS/MicroBlaze > with a path to an ASIC. > The configuration is done via a simple Tcl/Tk script and > the Makefile contains several targets. Works out-of-the-box > for available tragets. Adaption to a new FPGA board [2] took > me a few (some) hours - not so bad. > > What's your experience? > > Martin >
2 hours is correct, that what it usually takes to port LEON to new hardware. and the best thing is the LEON system can run FULL MMU enabled linux in spartan3 or any other low cost FPGA! Antti
Is it possible to use it without SRAM and only with SDRAM ?

"Antti Lukats" <antti@openchip.org> wrote in message 
news:dv1lus$iaa$1@online.de...
> "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> schrieb im Newsbeitrag > news:441451f8$0$11610$3b214f66@tunews.univie.ac.at... >> I'm wondering why there are so few messages about LEON [1] >> in this group. LEON looks like a very solid design (used >> by the ESA) and it is available in a GPL version. >> Could be a vendor independent replacement of NIOS/MicroBlaze >> with a path to an ASIC. >> The configuration is done via a simple Tcl/Tk script and >> the Makefile contains several targets. Works out-of-the-box >> for available tragets. Adaption to a new FPGA board [2] took >> me a few (some) hours - not so bad. >> >> What's your experience? >> >> Martin >> > > 2 hours is correct, that what it usually takes to port LEON to new > hardware. > > and the best thing is the LEON system can run FULL MMU enabled linux > in spartan3 or any other low cost FPGA! > > Antti >
"Jerome" <nospam@nospam.fr> schrieb im Newsbeitrag 
news:44145fdd$0$13024$626a54ce@news.free.fr...
> Is it possible to use it without SRAM and only with SDRAM ? >
well you need some initialized memory unless you are loading the sdram over jtag debugger basically, yes if you have means to load your application or bootloader into sdram there si no need for any other memories antti
In article <441451f8$0$11610$3b214f66@tunews.univie.ac.at>,
 "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> wrote:

> I'm wondering why there are so few messages about LEON [1] > in this group. LEON looks like a very solid design (used > by the ESA) and it is available in a GPL version. > Could be a vendor independent replacement of NIOS/MicroBlaze > with a path to an ASIC. > The configuration is done via a simple Tcl/Tk script and > the Makefile contains several targets. Works out-of-the-box > for available tragets. Adaption to a new FPGA board [2] took > me a few (some) hours - not so bad. > > What's your experience? > > Martin > > > [1] > http://www.gaisler.com/cms4_5_3/index.php?option=com_content&task=view&id=13&I > temid=53 > > [2] http://www.jopdesign.com/nios.jsp
its got its own ( yahoo based ) news group. And yes, its pretty cool.
Ok but  my concern is about R/W cycles assuming i want to use SDRAM for code 
execution or data storage.
Acessing SRAM is only 2  cycles (adr / data )
But for SDRAM , event with smart sdram controller , it will take more , no ?

"Antti Lukats" <antti@openchip.org> wrote in message 
news:dv1neh$l35$1@online.de...
> "Jerome" <nospam@nospam.fr> schrieb im Newsbeitrag > news:44145fdd$0$13024$626a54ce@news.free.fr... >> Is it possible to use it without SRAM and only with SDRAM ? >> > > well you need some initialized memory unless you are loading the sdram > over jtag debugger > > basically, yes if you have means to load your application or bootloader > into sdram > there si no need for any other memories > > antti >
"Jerome" <nospam@nospam.fr> schrieb im Newsbeitrag 
news:44147254$0$13020$626a54ce@news.free.fr...
> Ok but my concern is about R/W cycles assuming i want to use SDRAM for > code execution or data storage. > Acessing SRAM is only 2 cycles (adr / data ) > But for SDRAM , event with smart sdram controller , it will take more , no > ? > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dv1neh$l35$1@online.de... >> "Jerome" <nospam@nospam.fr> schrieb im Newsbeitrag >> news:44145fdd$0$13024$626a54ce@news.free.fr... >>> Is it possible to use it without SRAM and only with SDRAM ? >>> >> >> well you need some initialized memory unless you are loading the sdram >> over jtag debugger >> >> basically, yes if you have means to load your application or bootloader >> into sdram >> there si no need for any other memories >> >> antti >> > >
thats almost always so that ext(sdram) accesses are way slower cache helps to re-gain some cycles and improves performance but as sw is getting larger and doesnt fit into onchip memory so there are no options to use of sdram so if you can use BRAMs for cache only antti
Martin Schoeberl wrote:
> I'm wondering why there are so few messages about LEON [1] > in this group. LEON looks like a very solid design (used > by the ESA) and it is available in a GPL version. > Could be a vendor independent replacement of NIOS/MicroBlaze > with a path to an ASIC. > The configuration is done via a simple Tcl/Tk script and > the Makefile contains several targets. Works out-of-the-box > for available tragets. Adaption to a new FPGA board [2] took > me a few (some) hours - not so bad. > > What's your experience?
I keep meaning to try it, seeing as I share my first name with it. 8-) Leon
>well you need some initialized memory unless you are loading the sdram over >jtag debugger
Can you put the initial bits into the cache? (and setup the extra bits for the cache to say they are valid.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Hi,

you forgot to mention the MP (multiprocessor) support in LEON3 (up to 4 
microprocessors). Of course, you need to use the eCos version available 
for this MP system. I tested it 6 months ago and it works great. I think 
that now the support will be better than 6 months ago ;)

Regards,

Ivan


Martin Schoeberl wrote:
> I'm wondering why there are so few messages about LEON [1] > in this group. LEON looks like a very solid design (used > by the ESA) and it is available in a GPL version. > Could be a vendor independent replacement of NIOS/MicroBlaze > with a path to an ASIC. > The configuration is done via a simple Tcl/Tk script and > the Makefile contains several targets. Works out-of-the-box > for available tragets. Adaption to a new FPGA board [2] took > me a few (some) hours - not so bad. > > What's your experience? > > Martin > > > [1]
http://www.gaisler.com/cms4_5_3/index.php?option=com_content&task=view&id=13&Itemid=53
> > [2] http://www.jopdesign.com/nios.jsp > >