Question about multi write ports RAM in FPGA?

Hello,
Is that possible to make a multi write ports RAM in FPGA by using
distributed RAM or block RAM? It seems impossible to me. But using D
flip flop to implement the multi ports RAM will costs too much resouce.
Is there any suggestion to implement the multi write ports RAM in FPGA?
Thanks a lot.

fpga wrote:
> Hello,
> Is that possible to make a multi write ports RAM in FPGA by using
> distributed RAM or block RAM? It seems impossible to me. But using D
> flip flop to implement the multi ports RAM will costs too much resouce.
> Is there any suggestion to implement the multi write ports RAM in FPGA?
> Thanks a lot.

Xilinx has dual ported block RAM. In which both ports (I believe) can
do simultaneous writes.

If you want more ports than that then you may have to use time
multiplexing.

--------------------------------------------------------------------------------------------------------------
I am an EE student looking for summer employment in Toronto, Canada
area
If you have any openings please contact me at isaacb[AT]rogers[DOT]com.

Good catch, Isaac, you beat me to it.
Yes, BlockRAMs can write from both ports simultaneously, and the write
enable input can change from write to read on every clock tick.
Interestingly, ever write also performs a read of the same location,
either read-before-write or write-before-read. The former is more
useful.
For additional ports, use time multiplexing.
Peter Alfke

Thank you peter and Issac all. Yes, I want serverl read ports and
severl write ports for the RAM. So I think the only way I can do is to
use time multiplexing, which will limit the highest frequency I can
get.

If multi write means just 2 you are all set, if it means >2, besides
time based sharing you might also look at a recent (last week) thread
on incresing write ports by banking multiple BRAMs and using voting
logic. The difference between 1,2, 3+ is enormous if done in 1 clock. I
usually take several to mean >2.

See also Mar 6 "How do I make dual-port RAM from single port RAM?"

There were 2 interesting suggestions offered to allow 1 write port ASIC
rams to be used as an effective 2 port write ram but used 4 rams to do
this. The voting logic though still had to allow multi writes but is
only 1 bit wide. Perhaps these schemes can be used to allow >2 writes
per clock with even more voting logic. It will depend alot on your
reasons and conditions for wanting >2 writes. Typically high write
ports per clock are used in shallow datapath register files while low
write counts ports used in buffers etc.

What is your write port count and what is actual ram size and
application ?

John

Thanks very much, John. My ram size is 256x32 and I want it has 4 read
ports and 3 write ports. The ram is gonna to be used as the local
vector register file in my vector coprocessor. My vector coprocessor
has different function cores, each has its own local vector register
(LVR). So these LVR need to provide ports to the function unit(2 read
ports, 1 write ports) and ports for transfer LVR data between this
cores (2 read ports, 2 write ports). I choose 2 read ports and 2 write
ports for data transfering because I believe it can bring much better
performance than 1 read port/1 write port design.

Also, multiple ports RAM (I don't decide the size and ports number yet)
will be used as the register file in superscalar machine.

fpga wrote:

> Hello,
> Is that possible to make a multi write ports RAM in FPGA by using
> distributed RAM or block RAM? It seems impossible to me. But using D
> flip flop to implement the multi ports RAM will costs too much resouce.
> Is there any suggestion to implement the multi write ports RAM in FPGA?
> Thanks a lot.

BlockRAMs are the easiest for a dual-port write.

For a non-multiplexed multiport write using distributed RAM, a little 
extra logic and a bunch more distributed memories can give you what you 
need.

Each port in an n-port distributed RAM canfiguration has one write and 
n-1 read from each of the other memories.  A write is done with the 
desired write data and an XOR of all the other reads.  A read is done 
with a read of all the memories.  As long as there are never writes to 
the same port, this sytem works gret; I've used it for multi-channel 
flags on both sides of a synchronous interface.

As long as you have the asynchronous distributed memories and enough 
setup for the write address, read, and XOR before the data is written, 
it all flows.

Thank you very much.

Sorry I didn't clarify my requirement. I know it is easy for a
dual-port wirte and 1 wirte/multiple read RAM. But I need a RAM with >2
write ports and >2 read ports. Time-multiplexing is one choice, but it
may limited the system frequency.  Using voting logic as specified by
JJ maybe another choice.

fpga wrote:
> Thank you very much.
> 
> Sorry I didn't clarify my requirement. I know it is easy for a
> dual-port wirte and 1 wirte/multiple read RAM. But I need a RAM with >2
> write ports and >2 read ports. Time-multiplexing is one choice, but it
> may limited the system frequency.  Using voting logic as specified by
> JJ maybe another choice.

The method I suggested specifically works for your case.  You need a 
total of 9 dual-port distributed CLB SelectRAM memory sets for 3 Rd/Wr 
adresses and 1 Rd-only address.  If your 4 read addresses are unrelated 
to any of the 3 write addresses, you would end up with 6 dual-ports to 
support the 3 write ports and 3 dual-ports for each of your independent 
reads for a total of 18 dual-port CLB SelectRAM memory arrays.

For this to work, 1) you cannot write to the same location in more than 
one memory at the same time, 2) you have to XOR the input data with the 
data at the same location in memories related to the other write ports, 
and 3) your read values are the XORs of the data from each of the 
memories associated with the three write ports.

For a 4-bit with memory, assume the memories associated with the three 
write ports at entry 12 are

   MemA[12]==4'ha
   MemB[12]==4'h6
   MemC[12]==4'h0

Then a write to index 12 of Din==4'h7 at port B of your three-port write 
system would be

   MemB[12]<=(MemA[12]^MemC[12])^Din;
or
   MemB[12]<=(4'ha^4'h0)^4'h7;
which is
   MemB[12]<=4'hd;

So your following reads would be

   MemSys[12]==MemA[12]^MemB[12]^MemC[12];
or
   MemSys[12]==4'ha^4'hd^4'h0;
which is
   MemSys[12]==4'h7;

You wrote a value of 4'h7 into port B of your memory system and the 
later read of this location will be 4'h7.

If you want to have multiple writes to the same address location at the 
same time with the precedence set to a specific order, you can add 
additional logic to get the results you desire.

To fpga,
     Do you have any relationship with GN,pheonix. If no sorry for the
trouble.