Instantiating addsub, comparators in Xilinx

Thanks for all the reply! Will just leave it to synthesis then.

"Mike Treseler" <mike_treseler@comcast.net> wrote in message 
news:488cbhFih79fU1@individual.net...
> Leow Yuan Yeow wrote:
>> Hi, for a program such as
>> case state is
>> when S0=>
>>   A <= B + C;
>> when S1=>
>>   Z <= X + Y;
>> does it mean that 2 adders are generated, or will the synthesis recognize 
>> the adder can be shared?
>> Or to I have to specifically write a multiplexor for the adder? Thanks!
>
> There are no guarantees either way.
> But it doesn't really matter.
> There are not really any "adder" primitives
> inside the fpga. Only gates and flops.
>
> All synthesis guarantees is a netlist that
> simulates the same as the source code.
> There is no guarantee that the RTL or
> technology schematic output
> will look like I expect. But it will work.
>
> If I code for an input mux with
> one adder, I just might get two adders
> and an output mux, if that better
> matches the constraint settings or the whim
> of the synthesis algorithm.
> Or I might get just what I expect.
> Or I might get something completely different.
>
> Luckily, synthesis does a better
> job, on the average, of packing gates
> into a arbitrary device than I do.
>
>           -- Mike Treseler