Hi all, Did some company already implemented G.709 OTU-2 on Virtex-4 using the RocketIO? In other words: the maximum bitrate of RocketIO is 10.3125 but OTU-2 is 10.709. Should Virtex-4 be definitively excluded or are there some tricks to achieve that challenge? Cheers Mehdi
Virtex-4 RocketIO and G.709 OTU-2
Started by ●March 21, 2006
Reply by ●March 21, 20062006-03-21
Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : "Payload compatible only"), so no hope for OTU-2 I think. We have to wait Virtex-5 family ?
Reply by ●March 21, 20062006-03-21
GaLaKtIkUs� wrote:> Hi all, > Did some company already implemented G.709 OTU-2 on Virtex-4 using the > RocketIO? > In other words: the maximum bitrate of RocketIO is 10.3125 but OTU-2 is > 10.709. Should Virtex-4 be definitively excluded or are there some > tricks to achieve that challenge?I don't know about this protocol exactly, but for 10GBit Ethernet, which is a similar speed, you can use interfaces like XAUI (4x3.125Gbit) - if there is either a standard interface or a chip that could do this for you, then V4 could still be a contender. Jeremy
Reply by ●March 21, 20062006-03-21
On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote:>Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : >"Payload compatible only"), so no hope for OTU-2 I think. >We have to wait Virtex-5 family ?No. That is unlikely to have sufficient jitter performance, due to certain compromises that must be made when putting an MGT on an FPGA. In particular, it's likely to use a ring oscillator rather than an LC oscillator which would have better perfomance. Use an external SERDES designed for G.707 / G.709 work. Note that (before they discontinued it) Xilinx's standalone SERDES didn't meet the SONET jitter requirements either, so getting these things to work is clearly not a trivial task. Regards, Allan
Reply by ●March 22, 20062006-03-22
> Did some company already implemented G.709 OTU-2 on Virtex-4 using the > RocketIO?even if ... Does anyone really have those Virtex4 in that super-speedgrade -12X? To me it sounds like they won't be available anytime soon ... :-( bye, Michael
Reply by ●March 23, 20062006-03-23
Can you indicate me such a SERDES. It's perfect if its output is 64bits. Also it shoulden't do FEC stuff. FEC is planned to be done on FPGA. Thnaks in advance Mehdi Allan Herriman wrote:> On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote: > > >Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : > >"Payload compatible only"), so no hope for OTU-2 I think. > >We have to wait Virtex-5 family ? > > No. That is unlikely to have sufficient jitter performance, due to > certain compromises that must be made when putting an MGT on an FPGA. > In particular, it's likely to use a ring oscillator rather than an LC > oscillator which would have better perfomance. > > Use an external SERDES designed for G.707 / G.709 work. > > Note that (before they discontinued it) Xilinx's standalone SERDES > didn't meet the SONET jitter requirements either, so getting these > things to work is clearly not a trivial task. > > Regards, > Allan
Reply by ●March 23, 20062006-03-23
On 23 Mar 2006 06:22:37 -0800, "GaLaKtIkUs�" <taileb.mehdi@gmail.com> wrote:>Can you indicate me such a SERDES. It's perfect if its output is >64bits. Also it shoulden't do FEC stuff. FEC is planned to be done on >FPGA.Most 10Gb/s SERDES parts seem to have 16 bit interfaces, probably because there's common interface definition called SFI-4 that has 16 LVDS pairs clocked at 622-670MHz. Xilinx has an app note called XAPP 622 that describes how to implement such an interface on an FPGA. Did you use Google? You would have found SERDES manufacturers such as PMC, AMCC, Broadcom, etc.>Thnaks in advance >MehdiThanks for the top-post!> >Allan Herriman wrote: >> On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote: >> >> >Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : >> >"Payload compatible only"), so no hope for OTU-2 I think. >> >We have to wait Virtex-5 family ? >> >> No. That is unlikely to have sufficient jitter performance, due to >> certain compromises that must be made when putting an MGT on an FPGA. >> In particular, it's likely to use a ring oscillator rather than an LC >> oscillator which would have better perfomance. >> >> Use an external SERDES designed for G.707 / G.709 work. >> >> Note that (before they discontinued it) Xilinx's standalone SERDES >> didn't meet the SONET jitter requirements either, so getting these >> things to work is clearly not a trivial task. >> >> Regards, >> Allan
Reply by ●April 7, 20062006-04-07
Alain wrote:> Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : > "Payload compatible only"), so no hope for OTU-2 I think. > We have to wait Virtex-5 family ? >I have seen that note as well. Can someone explain what "Payload compatible only" means?
Reply by ●April 7, 20062006-04-07
Alain wrote:> Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf : > "Payload compatible only"), so no hope for OTU-2 I think. > We have to wait Virtex-5 family ? >I have seen that note as well. Can someone explain what "Payload compatible only" means?
Reply by ●April 7, 20062006-04-07
