For those who are interested, SUN released Open SPARC today: http://opensparc-t1.sunsource.net/download_hw.html Verilog RTL, verification and simulation tools included. Cheers. -- PabloBleyerKocik /"Person who say it cannot be done pablo / should not interrupt person doing it." @bleyer.org / -- Chinese proverb
OpenSPARC released
Started by ●March 21, 2006
Reply by ●March 21, 20062006-03-21
What's the betting that Antti is the first to get this going on an FPGA? Though I imagine it is huge when synthesized... Pablo Bleyer Kocik wrote:> For those who are interested, SUN released Open SPARC today: > > http://opensparc-t1.sunsource.net/download_hw.html > > Verilog RTL, verification and simulation tools included. > > Cheers. > > -- > PabloBleyerKocik /"Person who say it cannot be done > pablo / should not interrupt person doing it." > @bleyer.org / -- Chinese proverb
Reply by ●March 21, 20062006-03-21
John McGrath wrote:> What's the betting that Antti is the first to get this going on an > FPGA? > Though I imagine it is huge when synthesized...Has anyone seen Sizes / and MHz for this, finally sitting in a FPGA ? How does it compare with Leon ? -jg> > Pablo Bleyer Kocik wrote: > >>For those who are interested, SUN released Open SPARC today: >> >> http://opensparc-t1.sunsource.net/download_hw.html
Reply by ●March 22, 20062006-03-22
Hihi, I was thinking about that at the time of the first announcement (a few months ago), but well I will sure look at it, and decide what todo (if). but funny you asked, I am considering adopting some micro for one specific FPGA right now, but it would need to fit with SDRAM controller into 3000LUTs and there must be uclinux support for it. its very tight if doable using existing cores so I may end up re-writing something Antti
Reply by ●March 22, 20062006-03-22
Reply by ●March 22, 20062006-03-22
?? I wonder if there is any reason why it would be useful to compile the verilog for a FPGA? Austin Pablo Bleyer Kocik wrote:> For those who are interested, SUN released Open SPARC today: > > http://opensparc-t1.sunsource.net/download_hw.html > > Verilog RTL, verification and simulation tools included. > > Cheers. > > -- > PabloBleyerKocik /"Person who say it cannot be done > pablo / should not interrupt person doing it." > @bleyer.org / -- Chinese proverb >
Reply by ●March 22, 20062006-03-22
Austin Lesea wrote:> ?? > > I wonder if there is any reason why it would be useful to compile the > verilog for a FPGA? > > Austin > > Pablo Bleyer Kocik wrote: > > > For those who are interested, SUN released Open SPARC today: > > > > http://opensparc-t1.sunsource.net/download_hw.html > > > > Verilog RTL, verification and simulation tools included. > > > > Cheers. > > > > -- > > PabloBleyerKocik /"Person who say it cannot be done > > pablo / should not interrupt person doing it." > > @bleyer.org / -- Chinese proverb > >I can imagine no practical use. But it sure is fun to do :). -Isaac
Reply by ●March 23, 20062006-03-23
Errr... To start developing and testing a SoC based on OpenSPARC interfaced to a custom digital block in an FPGA? CPU cores + FPGA blocks seem to be resurrecting now. Also, a bunch of companies are working strongly on FPAAs and other analog configurable architectures (this time done right). If we have 8051/PSoC/ARM7/PowerPC embedded cores now, why we can't dream of having devices based on a state of the art and truly open platform (GPL) in the next years? And differently from the other proprietary solutions, anyone can share ownership and help in the development of OpenSPARC... -- PabloBleyerKocik /"But what... is it good for?" pablo / -- 1968 Engineer at IBM's Advanced Computing @bleyer.org / Systems Division, commenting on the microchip
Reply by ●March 23, 20062006-03-23
Weng Tianxiang wrote:> Hi Pablo, > Thank you for your useful information. > > WengThe problem is "System Requirements": "SPARC CPU based system"
Reply by ●March 23, 20062006-03-23
Michael wrote:> Weng Tianxiang wrote: > >>Hi Pablo, >>Thank you for your useful information. >> >>Weng > > > The problem is "System Requirements": "SPARC CPU based system" >Is that for the software development environment?. Seems like the verilog rtl code should be pretty generic. From the description it sounds more like a big compute farm engine rather than something you would put in a fpga for an embedded system. John Eaton
