How to write a correct code to do 2 writes to an array on same cycle?

Hi,

Here is a code segment showing 2 methods doing 2 writes to an array with  2 different addresses on the same cycle:

1. 
p1: process(CLK) is
begin
  if CLK'event and CLK = '1' then
    if C1 then
      An_Array(a) <= D1;
    end if;

    -- I know a /= b
    -- do I need to inform VHDL compiler of 2 different addresses?
    if C2 then
      An_Array(b) <= D2;  
    end if;
  end if;
end process;

2. 
p2: process(CLK) is
begin
  if CLK'event and CLK = '1' then
    case C1 & C2 is
      when "10" =>
        An_Array(a) <= D1;

      when "01" =>
        An_Array(b) <= D2;

      when "11" =>
        -- I know a /= b
        -- do I need to inform VHDL compiler of 2 different addresses?
        An_Array(a) <= D1;
        An_Array(b) <= D2;

      when others =>
        null;
    end case;
  end if;
end process;

I think it is no problem with a simulator.

Thank you.

Weng

  

On Tuesday, September 24, 2019 at 2:49:14 PM UTC-4, Weng Tianxiang wrote:
> Hi,
> 
> Here is a code segment showing 2 methods doing 2 writes to an array with  2 different addresses on the same cycle:
> 
> 1. 
> p1: process(CLK) is
> begin
>   if CLK'event and CLK = '1' then
>     if C1 then
>       An_Array(a) <= D1;
>     end if;
> 
>     -- I know a /= b
>     -- do I need to inform VHDL compiler of 2 different addresses?
>     if C2 then
>       An_Array(b) <= D2;  
>     end if;
>   end if;
> end process;

I think the short answer is YES, the compiler has no way of knowing you are writing to different array elements.  More importantly what hardware are you expecting this to synthesize?  Simulation is one thing, but I don't know this sort of construct is clear enough to produce any particular hardware.  Also, are you targeting an FPGA or a custom chip?  I expect there to potentially be a difference. 


> 2. 
> p2: process(CLK) is
> begin
>   if CLK'event and CLK = '1' then
>     case C1 & C2 is
>       when "10" =>
>         An_Array(a) <= D1;
> 
>       when "01" =>
>         An_Array(b) <= D2;
> 
>       when "11" =>
>         -- I know a /= b
>         -- do I need to inform VHDL compiler of 2 different addresses?
>         An_Array(a) <= D1;
>         An_Array(b) <= D2;
> 
>       when others =>
>         null;
>     end case;
>   end if;
> end process;
> 
> I think it is no problem with a simulator.

Again, the same issue.  I believe this code is equivalent to the first example.  The assignment statements tend to generate drivers and you may get two drivers on the address input to the array.  I expect you are intending to generate a dual port RAM with two separate inputs for address and data with separate write capability.  In FPGAs I use the sample code provided by the vendor to infer RAMs.  Even if I use my own code, I write the RAM code to be an independent module and then instantiate that.  

So what is your target? 

-- 

  Rick C.

  - Get 2,000 miles of free Supercharging
  - Tesla referral code - https://ts.la/richard11209

On Wednesday, September 25, 2019 at 9:00:37 AM UTC-7, Rick C wrote:
> On Tuesday, September 24, 2019 at 2:49:14 PM UTC-4, Weng Tianxiang wrote:
> > Hi,
> > 
> > Here is a code segment showing 2 methods doing 2 writes to an array with  2 different addresses on the same cycle:
> > 
> > 1. 
> > p1: process(CLK) is
> > begin
> >   if CLK'event and CLK = '1' then
> >     if C1 then
> >       An_Array(a) <= D1;
> >     end if;
> > 
> >     -- I know a /= b
> >     -- do I need to inform VHDL compiler of 2 different addresses?
> >     if C2 then
> >       An_Array(b) <= D2;  
> >     end if;
> >   end if;
> > end process;
> 
> I think the short answer is YES, the compiler has no way of knowing you are writing to different array elements.  More importantly what hardware are you expecting this to synthesize?  Simulation is one thing, but I don't know this sort of construct is clear enough to produce any particular hardware.  Also, are you targeting an FPGA or a custom chip?  I expect there to potentially be a difference. 
> 
> 
> > 2. 
> > p2: process(CLK) is
> > begin
> >   if CLK'event and CLK = '1' then
> >     case C1 & C2 is
> >       when "10" =>
> >         An_Array(a) <= D1;
> > 
> >       when "01" =>
> >         An_Array(b) <= D2;
> > 
> >       when "11" =>
> >         -- I know a /= b
> >         -- do I need to inform VHDL compiler of 2 different addresses?
> >         An_Array(a) <= D1;
> >         An_Array(b) <= D2;
> > 
> >       when others =>
> >         null;
> >     end case;
> >   end if;
> > end process;
> > 
> > I think it is no problem with a simulator.
> 
> Again, the same issue.  I believe this code is equivalent to the first example.  The assignment statements tend to generate drivers and you may get two drivers on the address input to the array.  I expect you are intending to generate a dual port RAM with two separate inputs for address and data with separate write capability.  In FPGAs I use the sample code provided by the vendor to infer RAMs.  Even if I use my own code, I write the RAM code to be an independent module and then instantiate that.  
> 
> So what is your target? 
> 
> -- 
> 
>   Rick C.
> 
>   - Get 2,000 miles of free Supercharging
>   - Tesla referral code - https://ts.la/richard11209

Hi Rick,

Thank you for your answer.

Actually I am writing code not targeting any FPGA manufactures, neither Altera nor Xilinx, I just want that the code can be simulated by Mentor simulator to prove that my algorithm on a universal subject is working IN THEORY: with 2 write ports for an array, everything is working. By doing so it will save me a lot of energy, cost and time. 

Translating 2 writes at 2 different addresses for an array in code to a 2 write port memory is considered as a mature technology like to implement an 64-bit adder if one decides to select a FPGA chip to implement.

I think based on the definition in a sequential process with or without clock, my code is working: if conditions C1 = '1' and C2 = '1', first the simulator by definition executes An_Array(a) <= D1; then An_Array(b) <= D2; because a /= b, so An_Array gets its 2 writes without any problem in simulation.

I know if I want the code to be executed on an Altera chip or a Xilinx chip, I have to use one of multiple possible 2 writes memory mechanisms to implement the code. But at this stage, I don't want to spend time doing it.

At this stage, I think I don't have to put consideration to it.

Weng

On Wednesday, September 25, 2019 at 1:31:35 PM UTC-4, Weng Tianxiang wrote:
> On Wednesday, September 25, 2019 at 9:00:37 AM UTC-7, Rick C wrote:
> > On Tuesday, September 24, 2019 at 2:49:14 PM UTC-4, Weng Tianxiang=20
>=20
> I just want that the code can be simulated by Mentor simulator to prove t=
hat my algorithm on a universal subject is working IN THEORY: with 2 write =
ports for an array, everything is working. By doing so it will save me a lo=
t of energy, cost and time.=20

So, you want someone else to run a VHDL simulator for you in order to save =
you a lot of energy, cost and time?  Ummm...why, are you being lazy?  I can=
 pretty much guarantee that any VHDL simulator will properly execute the co=
de that you've written per the VHDL language standard.  Whether that code p=
erforms the function that you would like it for your "algorithm on a univer=
sal subject" is up to you to decide.  Best of luck on your new endeavors.

Kevin Jennings

On Wednesday, September 25, 2019 at 10:47:04 AM UTC-7, KJ wrote:
> On Wednesday, September 25, 2019 at 1:31:35 PM UTC-4, Weng Tianxiang wrote:
> > On Wednesday, September 25, 2019 at 9:00:37 AM UTC-7, Rick C wrote:
> > > On Tuesday, September 24, 2019 at 2:49:14 PM UTC-4, Weng Tianxiang 
> > 
> > I just want that the code can be simulated by Mentor simulator to prove that my algorithm on a universal subject is working IN THEORY: with 2 write ports for an array, everything is working. By doing so it will save me a lot of energy, cost and time. 
> 
> So, you want someone else to run a VHDL simulator for you in order to save you a lot of energy, cost and time?  Ummm...why, are you being lazy?  I can pretty much guarantee that any VHDL simulator will properly execute the code that you've written per the VHDL language standard.  Whether that code performs the function that you would like it for your "algorithm on a universal subject" is up to you to decide.  Best of luck on your new endeavors.
> 
> Kevin Jennings

Hi KJ,

I never said that: "So, you want someone else to run a VHDL simulator for you in order to save you a lot of energy, cost and time?"

I will do the simulation by myself to determine if the algorithm is correct.

And I will let others to test if the code implementation on either a Xilinx chip or an Altera chip is working. 

A 2 write port memory is a mature technique and I don't have to spend a lot of time to do it myself.

Thank you.

Weng

On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wrote:
> 
> I never said that: "So, you want someone else to run a VHDL simulator for you in order to save you a lot of energy, cost and time?"
> 
I paraphrased slightly, but yes you did say that.  Read your original post which I quoted you on.

> I will do the simulation by myself to determine if the algorithm is correct.

Cool.
> 
> And I will let others to test if the code implementation on either a Xilinx chip or an Altera chip is working. 
> 
Beyond a superficial, quick code review, why would anyone want to do that?

> A 2 write port memory is a mature technique and I don't have to spend a lot of time to do it myself.
> 
And yet here you are, writing up your own code for two write port memory which you say "is a mature technique".  That's pretty much the definition of re-inventing the wheel.

Kevin Jennings

On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote:
> On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wrote:
> > 
> > I never said that: "So, you want someone else to run a VHDL simulator for you in order to save you a lot of energy, cost and time?"
> > 
> I paraphrased slightly, but yes you did say that.  Read your original post which I quoted you on.
> 
> > I will do the simulation by myself to determine if the algorithm is correct.
> 
> Cool.
> > 
> > And I will let others to test if the code implementation on either a Xilinx chip or an Altera chip is working. 
> > 
> Beyond a superficial, quick code review, why would anyone want to do that?
> 
> > A 2 write port memory is a mature technique and I don't have to spend a lot of time to do it myself.
> > 
> And yet here you are, writing up your own code for two write port memory which you say "is a mature technique".  That's pretty much the definition of re-inventing the wheel.
> 
> Kevin Jennings

KJ,

I prefer for VHDL grammar to introduce a new statement, specifying an if statement is a second write to an array. Here is a code example on how to introduce such statement:

Here is a code segment showing method, doing 2 writes to an array with 2 different addresses on the same cycle:

p1: process(CLK) is
begin
  if CLK'event and CLK = '1' then
    if C1 then
      An_Array(a) <= D1;
    end if;

    -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.
 
    if_2 C2 then
      An_Array(b) <= D2;  
    end if;
  end if;
end process;

Using the new suggested keyword "if_2" in VHDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chip.

In my design there are more than 10 arrays need 2-write port memory.

Weng

On 25/09/2019 22:22, Weng Tianxiang wrote:
> On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote:
>> On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wrote:
..
> p1: process(CLK) is
> begin
>    if CLK'event and CLK = '1' then
>      if C1 then
>        An_Array(a) <= D1;
>      end if;
> 
>      -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.
>   
>      if_2 C2 then
>        An_Array(b) <= D2;
>      end if;
>    end if;
> end process;
> 
> Using the new suggested keyword "if_2" in VHDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chip.
> 
> In my design there are more than 10 arrays need 2-write port memory.
> 
> Weng
> 

Hi Weng,

Give it up, your are flogging a dead horse, no new language constructs 
are requires as we already have the correct simulation and synthesis 
models for decades.

If you have lots of dual port memories to connect use a Generate statement.

Regards,
Hans
www.ht-lab.com

On Wednesday, September 25, 2019 at 5:22:34 PM UTC-4, Weng Tianxiang wrote:
> On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote:
> > On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wrote:
> 
> I prefer for VHDL grammar to introduce a new statement, specifying an if statement is a second write to an array. 
'I prefer' is not justification.  One needs to provide objective, measurable improvement.  'I prefer' doesn't do it.

> Here is a code example on how to introduce such statement:
Yet your example by one measure shows how your new method is worse.  Rather than simply typing 'if', now one types 'if_2'.  How is that better?  The same simulation and synthesis results would occur but now any designer is typing more to achieve the same...sort of unproductive don't you think?  The language gets more complex and produces no objective benefit to anyone...not the sort of change that benefits.

> 
> Using the new suggested keyword "if_2" in VHDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chip.
> 
Everybody?  How about anybody besides you? Who are these people that "repeatedly to write a 2-write-port memory" rather than writing it once?  Those people need to learn how design should be done.

> In my design there are more than 10 arrays need 2-write port memory.
> 
This statement simply demonstrates your total lack of ability in design.  If you're writing the same thing 10 times you're doing it the wrong way.

Kevin Jennings

On Thursday, September 26, 2019 at 2:50:48 AM UTC-7, HT-Lab wrote:
> On 25/09/2019 22:22, Weng Tianxiang wrote:
> > On Wednesday, September 25, 2019 at 12:34:13 PM UTC-7, KJ wrote:
> >> On Wednesday, September 25, 2019 at 2:07:45 PM UTC-4, Weng Tianxiang wrote:
> ..
> > p1: process(CLK) is
> > begin
> >    if CLK'event and CLK = '1' then
> >      if C1 then
> >        An_Array(a) <= D1;
> >      end if;
> > 
> >      -- "IF_2" is a new keyword which introduces a second write to an array in its full range, including all "else", "elsif" parts. And "if_2" keyword can only be used in a clocked process.
> >   
> >      if_2 C2 then
> >        An_Array(b) <= D2;
> >      end if;
> >    end if;
> > end process;
> > 
> > Using the new suggested keyword "if_2" in VHDL, everybody would like it, not having repeatedly to write a 2-write-port memory for different FPGA chip.
> > 
> > In my design there are more than 10 arrays need 2-write port memory.
> > 
> > Weng
> > 
> 
> Hi Weng,
> 
> Give it up, your are flogging a dead horse, no new language constructs 
> are requires as we already have the correct simulation and synthesis 
> models for decades.
> 
> If you have lots of dual port memories to connect use a Generate statement.
> 
> Regards,
> Hans
> www.ht-lab.com

Hans,

Here is an excellent paper dealing with the situation: efficient multi-port memory with FPGA, http://www.eecg.toronto.edu/~steffan/papers/laforest_fpga10.pdf.

I appreciate the paper very much. I know there is a solution to 2-write memory, but simple "if_2" is a simple solution to inferring to the method.

Weng