We're planning a new universal boot loader for a family of ST processors. The uP would host the loader in a bit of local flash and read an outboard serial flash to get the specific application code and one or more FPGA configurations. So, how many config bits might there be for a modern mid-range FPGA doing a moderately complex application? I think we could enable compression too. Please consider this a PHB type question. I don't do FPGA development myself, past whiteboarding. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
FPGA config sizes
Started by ●November 8, 2019
Reply by ●November 8, 20192019-11-08
Am 08.11.19 um 20:08 schrieb John Larkin:> > > We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding. >The size of the programming file is in the data sheet. It is constant and does not depend on the implemented circuitry. Newer FPGAs may allow to program only some sectors of the chip. regards, Gerhard
Reply by ●November 8, 20192019-11-08
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:> We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding.Anyone know what a "PHB type question" is? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
Reply by ●November 8, 20192019-11-08
On 08/11/2019 19:08, John Larkin wrote:> > > We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding. >The uncompressed FPGA configuration file size does not change with the device utilization. You need to look at the data sheet for the particular device. Obviously the compressed file size will be variable - with anything from 0% to near 100% compression ratio dependent on content and compression algorithm.
Reply by ●November 8, 20192019-11-08
On Friday, November 8, 2019 at 1:09:04 PM UTC-6, John Larkin wrote:> We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding. > > -- > > John Larkin Highland Technology, Inc > picosecond timing precision measurement > > jlarkin att highlandtechnology dott com > http://www.highlandtechnology.comThere's a general trend of about 60-80 bits per LUT input (can go higher). 4LUT has ~4-6 inputs, 6LUT or ALM 6-8 inputs. Count the number of LUTs in the part and multiply. Some go as high as 400M+ configuration bits. Jim Brakefield
Reply by ●November 8, 20192019-11-08
On 2019-11-08 Rick C wrote in comp.arch.fpga:> On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote: >> >> Please consider this a PHB type question. I don't do FPGA development >> myself, past whiteboarding. > > Anyone know what a "PHB type question" is?https://dilbert.com/search_results?terms=phb -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Corry's Law: Paper is always strongest at the perforations.
Reply by ●November 8, 20192019-11-08
On Friday, November 8, 2019 at 5:48:04 PM UTC-5, Stef wrote:> On 2019-11-08 Rick C wrote in comp.arch.fpga: > > On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote: > >> > >> Please consider this a PHB type question. I don't do FPGA development > >> myself, past whiteboarding. > > > > Anyone know what a "PHB type question" is? > > https://dilbert.com/search_results?terms=phbYeah, someone explained in the other group. A bit obscure, methinks. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
Reply by ●November 9, 20192019-11-09
On 08/11/2019 19:08, John Larkin wrote:> > > We're planning a new universal boot loader for a family of ST > processors. The uP would host the loader in a bit of local flash and > read an outboard serial flash to get the specific application code and > one or more FPGA configurations. > > So, how many config bits might there be for a modern mid-range FPGA > doing a moderately complex application? > > I think we could enable compression too. > > Please consider this a PHB type question. I don't do FPGA development > myself, past whiteboarding. >From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039. LFE5-45 - 8.86Mb From Xilinx UG470 Xilinx Artix 35T and 50T need the same 17.536 Mb MK
Reply by ●November 9, 20192019-11-09
On 09/11/2019 09:49, Michael Kellett wrote:> On 08/11/2019 19:08, John Larkin wrote: >> >> >> We're planning a new universal boot loader for a family of ST >> processors. The uP would host the loader in a bit of local flash and >> read an outboard serial flash to get the specific application code and >> one or more FPGA configurations. >> >> So, how many config bits might there be for a modern mid-range FPGA >> doing a moderately complex application? >> >> I think we could enable compression too. >> >> Please consider this a PHB type question. I don't do FPGA development >> myself, past whiteboarding. >> > From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039. > > LFE5-45 - 8.86Mb > > > From Xilinx UG470 > Xilinx Artix 35T and 50T need the same 17.536 Mb > > MKWhy complicate things with memory soooo cheap ??? Just store raw data...
Reply by ●November 9, 20192019-11-09
On Sat, 9 Nov 2019 11:15:56 +0000, TTman <kraken.sankey@gmail.com> wrote:>On 09/11/2019 09:49, Michael Kellett wrote: >> On 08/11/2019 19:08, John Larkin wrote: >>> >>> >>> We're planning a new universal boot loader for a family of ST >>> processors. The uP would host the loader in a bit of local flash and >>> read an outboard serial flash to get the specific application code and >>> one or more FPGA configurations. >>> >>> So, how many config bits might there be for a modern mid-range FPGA >>> doing a moderately complex application? >>> >>> I think we could enable compression too. >>> >>> Please consider this a PHB type question. I don't do FPGA development >>> myself, past whiteboarding. >>> >> From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039. >> >> LFE5-45 - 8.86Mb >> >> >> From Xilinx UG470 >> Xilinx Artix 35T and 50T need the same 17.536 Mb >> >> MK >Why complicate things with memory soooo cheap ??? Just store raw data...Compression could save bootup time. The Artix7 that I'm using now is only 17 mbits, but some of the Vertix chips are approaching a gigabit. Luckily, I can't afford them. https://www.digikey.com/product-detail/en/xilinx-inc/XCVU37P-3FSVH2892E/122-XCVU37P-3FSVH2892E-ND/10445719 Probably lots of config bits. -- John Larkin Highland Technology, Inc lunatic fringe electronics
