CPU Softcore Compendium

Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per clock and a performance metric incorporating all three.  I don't recall the author's name, but it was amazingly complete.  

Anyone remember that?  Still got the link? 

-- 

  Rick C.

  - Get 1,000 miles of free Supercharging
  - Tesla referral code - https://ts.la/richard11209

On Thursday, April 16, 2020 at 11:14:19 AM UTC-5, Rick C wrote:
> Some time ago a link was posted here to a very comprehensive list of soft=
 CPU designs which included LUT counts, clock rates, instructions per clock=
 and a performance metric incorporating all three.  I don't recall the auth=
or's name, but it was amazingly complete. =20
>=20
> Anyone remember that?  Still got the link?=20
>=20
> --=20
>=20
>   Rick C.
>=20
>   - Get 1,000 miles of free Supercharging
>   - Tesla referral code - https://ts.la/richard11209

https://opencores.org/projects/up_core_list/summary

Several legacy processors are listed:
https://opencores.org/projects/up_core_list/downloads
uP_core_list_by_style-clone190221.pdf

Also look into MISTer as it supports several legacy systems.
None are competitive speed wise with high performance uP.

With LUTs costing less than $0.001 each some soft core uPs are inexpensive,=
 free if you have unused LUTs and block RAMs.
For debug, changing block RAM contents is much faster than rerunning the FP=
GA design.

> > Some time ago a link was posted here to a very comprehensive list of soft CPU designs which included LUT counts, clock rates, instructions per clock and a performance metric incorporating all three.  I don't recall the author's name, but it was amazingly complete.  
> > 
> > Anyone remember that?  Still got the link? 

> https://opencores.org/projects/up_core_list/summary
> 

Hey, wow, even our ERIC5 is in there! (Unfortunately, they misspelled our homepage... Correct is: www.entner-electronics.com)

On Sunday, June 28, 2020 at 10:56:11 AM UTC-5, thomas....@gmail.com wrote:
> > > Some time ago a link was posted here to a very comprehensive list of =
soft CPU designs which included LUT counts, clock rates, instructions per c=
lock and a performance metric incorporating all three.  I don't recall the =
author's name, but it was amazingly complete. =20
> > >=20
> > > Anyone remember that?  Still got the link?=20
>=20
> > https://opencores.org/projects/up_core_list/summary
> >=20
>=20
> Hey, wow, even our ERIC5 is in there! (Unfortunately, they misspelled our=
 homepage... Correct is: www.entner-electronics.com)

Ugh, could use more recent FPGA LUT counts and Fmax for the the Eric5?

Am starting to get comfortable with Vivado.  Want to get updated resource u=
sage on newer parts (16nm parts supported by Webpack version of Vivado).
So far Vivado is not inferring block RAMs like ISE did?
Am getting 50-60% better Fmax for Zynq-US+ over Kintex-7 parts.

Jim Brakefield

On Tuesday, June 30, 2020 at 9:15:32 PM UTC-5, jim.br...@ieee.org wrote:
> On Sunday, June 28, 2020 at 10:56:11 AM UTC-5, thomas....@gmail.com wrote=
:
> > > > Some time ago a link was posted here to a very comprehensive list o=
f soft CPU designs which included LUT counts, clock rates, instructions per=
 clock and a performance metric incorporating all three.  I don't recall th=
e author's name, but it was amazingly complete. =20
> > > >=20
> > > > Anyone remember that?  Still got the link?=20
> >=20
> > > https://opencores.org/projects/up_core_list/summary
> > >=20
> >=20
> > Hey, wow, even our ERIC5 is in there! (Unfortunately, they misspelled o=
ur homepage... Correct is: www.entner-electronics.com)
>=20
> Ugh, could use more recent FPGA LUT counts and Fmax for the the Eric5?
>=20
> Am starting to get comfortable with Vivado.  Want to get updated resource=
 usage on newer parts (16nm parts supported by Webpack version of Vivado).
> So far Vivado is not inferring block RAMs like ISE did?
> Am getting 50-60% better Fmax for Zynq-US+ over Kintex-7 parts.
>=20
> Jim Brakefield

Ugh, getting familiar with Vivado:
Truly timing driven place & route: with timing driven synthesis!
Will use LUT RAM instead of block RAM if it is faster.
So will switch to area optimized flow so block RAM is usually preferred to =
LUT RAM.=20