deglitching a clock

On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote:


>So the Fpga to Fpga routing worked - good.

That's not what we did. We designed a clock deglitcher to go inside
the FPGA.

John

John Larkin wrote:
> On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote:
>
>
> >So the Fpga to Fpga routing worked - good.
>
> That's not what we did. We designed a clock deglitcher to go inside
> the FPGA.

Enough propagation delays to cover the dwell at the switching
threshold, and a state machine to make sure that the clock only changes
state once in that interval?

-- 
Bill Sloman, Nijmegen

On 29 Mar 2006 01:00:59 -0800, bill.sloman@ieee.org wrote:

>
>John Larkin wrote:
>> On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote:
>>
>>
>> >So the Fpga to Fpga routing worked - good.
>>
>> That's not what we did. We designed a clock deglitcher to go inside
>> the FPGA.
>
>Enough propagation delays to cover the dwell at the switching
>threshold, and a state machine to make sure that the clock only changes
>state once in that interval?


We did my original #2 suggestion, a tapped delay line driven from the
pin, driving an r-s flipflop. Set the flop if all the taps are 1s,
clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter.
The delay line is a string of eight buffers, about 10 ns overall.

We'd have done Peter's circuit if we'd learned of it sooner.

It's interesting that my post evoked two classes of response:

1. It can't be done, don't do it, kluge the boards (also the official
Xilinx response!)

2. Yes, and here are my ideas on how you could do it/how I've already
done it/interesting asides.

John

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:i88l229so8qheephlt41crc0v7e5ebch3r@4ax.com...
> On 29 Mar 2006 01:00:59 -0800, bill.sloman@ieee.org wrote:
>
>>
>>John Larkin wrote:
>>> On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote:
>>>
>>>
>>> >So the Fpga to Fpga routing worked - good.
>>>
>>> That's not what we did. We designed a clock deglitcher to go inside
>>> the FPGA.
>>
>>Enough propagation delays to cover the dwell at the switching
>>threshold, and a state machine to make sure that the clock only changes
>>state once in that interval?
>
>
> We did my original #2 suggestion, a tapped delay line driven from the
> pin, driving an r-s flipflop. Set the flop if all the taps are 1s,
> clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter.
> The delay line is a string of eight buffers, about 10 ns overall.
>
> We'd have done Peter's circuit if we'd learned of it sooner.
>
> It's interesting that my post evoked two classes of response:
>
> 1. It can't be done, don't do it, kluge the boards (also the official
> Xilinx response!)
>
> 2. Yes, and here are my ideas on how you could do it/how I've already
> done it/interesting asides.
>
> John
>
>

'We tried that before and it didn't work'

'OK, what did you try before'

'He was very good and proved it didn't work with some maths type stuff and 
it didn't work'

'Yes, but what did he try'

'It didn't work'

'But, what was it'

'It didn't work'

'Have you got the information about it'

'Err, no, err hang on.'

Waits a while. Mouldy thing arrives.

'There you go, see doesn't work'

'OK, let me have a look'

Goes away for a bit of.....

Comes back

'So, the problem is he did it like this'

'Doesn't work'

'Yes... but if you do it like this' Spends some time explaining....

'He was very clever, see... here's the math, it doesn't work. We've tried it 
before and it doesn't work'

'OK, but if you do it like this then it will work'

'No, we've already tried it and it doesn't work'

'You've tried it the way that I'm suggesting'

'Pardon'

'This way'

'Erm, he was very clever. Look, if you take some time then you can see that 
it doesn't work... How did you answer the 'Where do you see yourself in five 
years time' question at the interviev?'

DNA

"Genome" <ilike_spam@yahoo.co.uk> a &#4294967295;crit dans le message de
news:sLCWf.25632$Nh7.15570@newsfe4-win.ntli.net...
>
> "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in
message
> news:i88l229so8qheephlt41crc0v7e5ebch3r@4ax.com...
> > On 29 Mar 2006 01:00:59 -0800, bill.sloman@ieee.org wrote:
> >
> >>
> >>John Larkin wrote:
> >>> On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote:
> >>>
> >>>
> >>> >So the Fpga to Fpga routing worked - good.
> >>>
> >>> That's not what we did. We designed a clock deglitcher to go inside
> >>> the FPGA.
> >>
> >>Enough propagation delays to cover the dwell at the switching
> >>threshold, and a state machine to make sure that the clock only changes
> >>state once in that interval?
> >
> >
> > We did my original #2 suggestion, a tapped delay line driven from the
> > pin, driving an r-s flipflop. Set the flop if all the taps are 1s,
> > clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter.
> > The delay line is a string of eight buffers, about 10 ns overall.
> >
> > We'd have done Peter's circuit if we'd learned of it sooner.
> >
> > It's interesting that my post evoked two classes of response:
> >
> > 1. It can't be done, don't do it, kluge the boards (also the official
> > Xilinx response!)
> >
> > 2. Yes, and here are my ideas on how you could do it/how I've already
> > done it/interesting asides.
> >
> > John
> >
> >
>
> 'We tried that before and it didn't work'
>
> 'OK, what did you try before'
>
> 'He was very good and proved it didn't work with some maths type stuff and
> it didn't work'
>
> 'Yes, but what did he try'
>
> 'It didn't work'
>
> 'But, what was it'
>
> 'It didn't work'
>
> 'Have you got the information about it'
>
> 'Err, no, err hang on.'
>
> Waits a while. Mouldy thing arrives.
>
> 'There you go, see doesn't work'
>
> 'OK, let me have a look'
>
> Goes away for a bit of.....
>
> Comes back
>
> 'So, the problem is he did it like this'
>
> 'Doesn't work'
>
> 'Yes... but if you do it like this' Spends some time explaining....
>
> 'He was very clever, see... here's the math, it doesn't work. We've tried
it
> before and it doesn't work'
>
> 'OK, but if you do it like this then it will work'
>
> 'No, we've already tried it and it doesn't work'
>
> 'You've tried it the way that I'm suggesting'
>
> 'Pardon'
>
> 'This way'
>
> 'Erm, he was very clever. Look, if you take some time then you can see
that
> it doesn't work... How did you answer the 'Where do you see yourself in
five
> years time' question at the interviev?'
>

ROFL.


- OK, but I don't understand why it can't work. Please let me try and learn
by myself why it can't.
...
...
- Oh, but you made it work. How can it be?
- Oh. That's pretty simple: I just didn't know it couldn't work :-)

-- 
Thanks,
Fred.

Fred Bartoli schrieb:

> ROFL.

Yep. But try better quoting.

> 
> - OK, but I don't understand why it can't work. Please let me try and learn
> by myself why it can't.
> ...
> ...
> - Oh, but you made it work. How can it be?
> - Oh. That's pretty simple: I just didn't know it couldn't work :-)

I just saw a nice TV show, which ended with the words.

Theory is the thing you can't understand.
Practice is the thing you can't explain.

Regards
Falk

Put me *SQUARELY* in category 1.  You have a HW problem that demands a
re-layout.  The kludges presented here may work for quantity 1, but you
will have trouble trying to build many of these.  And this approach is
wholly unacceptable for a product that will ship to customers.
'Deglitchers' are for mechanical switches, not clocks.

There are some basic elements that must work on a digital circuit
board, and the 'clock' falls into this category.

Hello John,

> 
> We did my original #2 suggestion, a tapped delay line driven from the
> pin, driving an r-s flipflop. Set the flop if all the taps are 1s,
> clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter.
> The delay line is a string of eight buffers, about 10 ns overall.
> 
> We'd have done Peter's circuit if we'd learned of it sooner.
> 
> It's interesting that my post evoked two classes of response:
> 
> 1. It can't be done, don't do it, kluge the boards (also the official
> Xilinx response!)
> 
> 2. Yes, and here are my ideas on how you could do it/how I've already
> done it/interesting asides.
> 

That probably depends on what kinds of projects the individual 
responders usually work on. In my field (medical) I could lose my shirt 
if I did the digital de-glitcher thing. If it's an application where 
nothing bad can happen when it chokes or where that condition will 
always be signaled it might be different. But I wouldn't do it.

Regards, Joerg

http://www.analogconsultants.com

John,

I assume before this that the clock was going into a global clock pin?  If 
so, how do you deal with losing the low skew chip-wide network now that 
you're coming in on a standard I/O pin?

Take care,
Rob

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:i88l229so8qheephlt41crc0v7e5ebch3r@4ax.com...
> On 29 Mar 2006 01:00:59 -0800, bill.sloman@ieee.org wrote:
>
>>
>>John Larkin wrote:
>>> On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote:
>>>
>>>
>>> >So the Fpga to Fpga routing worked - good.
>>>
>>> That's not what we did. We designed a clock deglitcher to go inside
>>> the FPGA.
>>
>>Enough propagation delays to cover the dwell at the switching
>>threshold, and a state machine to make sure that the clock only changes
>>state once in that interval?
>
>
> We did my original #2 suggestion, a tapped delay line driven from the
> pin, driving an r-s flipflop. Set the flop if all the taps are 1s,
> clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter.
> The delay line is a string of eight buffers, about 10 ns overall.
>
> We'd have done Peter's circuit if we'd learned of it sooner.
>
> It's interesting that my post evoked two classes of response:
>
> 1. It can't be done, don't do it, kluge the boards (also the official
> Xilinx response!)
>
> 2. Yes, and here are my ideas on how you could do it/how I've already
> done it/interesting asides.
>
> John
>
> 

John Larkin wrote:
> On 29 Mar 2006 01:00:59 -0800, bill.sloman@ieee.org wrote:
> 
> 
>>John Larkin wrote:
>>
>>>On 28 Mar 2006 12:45:23 -0800, bill.sloman@ieee.org wrote:
>>>
>>>
>>>
>>>>So the Fpga to Fpga routing worked - good.
>>>
>>>That's not what we did. We designed a clock deglitcher to go inside
>>>the FPGA.
>>
>>Enough propagation delays to cover the dwell at the switching
>>threshold, and a state machine to make sure that the clock only changes
>>state once in that interval?
> 
> 
> 
> We did my original #2 suggestion, a tapped delay line driven from the
> pin, driving an r-s flipflop. Set the flop if all the taps are 1s,
> clear it if all are 0s. Sort of a poor man's 1-bit FIR lowpass filter.
> The delay line is a string of eight buffers, about 10 ns overall.
> 
> We'd have done Peter's circuit if we'd learned of it sooner.
> 
> It's interesting that my post evoked two classes of response:
> 
> 1. It can't be done, don't do it, kluge the boards (also the official
> Xilinx response!)
> 
> 2. Yes, and here are my ideas on how you could do it/how I've already
> done it/interesting asides.

A couple of questions for those who are in 1),

  Would you use the Pin-Delay feature on a FPGA, to de-skew click lines 
from other devices ?

  If you are OK with that, suppose John now uses the same Pin-delay 
feature (chained) on his 'toggle rate governer' - is that then OK ?

-jg