Hi all, I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm currently getting an error 1.11.3, which says I didn't increment the ABus correctly during seqAddr bus access. The particular case I'm looking at is this: ABus = 32'h00000E69, and BE = 4'b0111, using sequential address, byte-enable transfer, and xfer_size is "byte." The slave I wrote into is a full-word device that supports byte-enable. So, there shouldn't be any need for conversion cycles, and so my next ABus is 0x00000E6C. But apparently the OPB monitor flags this as an error. I think it expects the ABus to be incremented only by 1, since the previous xfer_size is byte. I think this is correct _if_ I'm using the basic dynamic sizing and _not_ the byte-enable architecture. Digging into the OPB monitor code, it seems that the process that checks for this particular scenario only checks for the xfer_sizes and xfer_acks - there's no references to byte-enable signals. The OPB monitor version I have is 2.0.1, and it seems to be the latest version that you can get from Xilinx. Any help / input is greatly appreciated. Thanks, dumak23
OPB monitor error
Started by ●March 28, 2006
Reply by ●March 28, 20062006-03-28
Hi dumak23 this looks wrong to me "ABus = 32'h00000E69, and BE = 4'b0111" is this a typo? you have 3 byte lanes enabled, I'm not an OPB expert but I think it should be 4'b1000 Aurash dumak23@yahoo.com wrote:> Hi all, > > I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm > currently getting an error 1.11.3, which says I didn't increment the > ABus correctly during seqAddr bus access. The particular case I'm > looking at is this: ABus = 32'h00000E69, and BE = 4'b0111, using > sequential address, byte-enable transfer, and xfer_size is "byte." The > slave I wrote into is a full-word device that supports byte-enable. So, > there shouldn't be any need for conversion cycles, and so my next ABus > is 0x00000E6C. But apparently the OPB monitor flags this as an error. I > think it expects the ABus to be incremented only by 1, since the > previous xfer_size is byte. I think this is correct _if_ I'm using the > basic dynamic sizing and _not_ the byte-enable architecture. > > Digging into the OPB monitor code, it seems that the process that > checks for this particular scenario only checks for the xfer_sizes and > xfer_acks - there's no references to byte-enable signals. The OPB > monitor version I have is 2.0.1, and it seems to be the latest version > that you can get from Xilinx. > > Any help / input is greatly appreciated. > > Thanks, > > dumak23 >
Reply by ●March 28, 20062006-03-28
dumak23@yahoo.com wrote:> Hi all, > > I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm > currently getting an error 1.11.3, which says I didn't increment the > ABus correctly during seqAddr bus access. The particular case I'm > looking at is this: ABus = 32'h00000E69, and BE = 4'b0111, using > sequential address, byte-enable transfer, and xfer_size is "byte." The > slave I wrote into is a full-word device that supports byte-enable. So, > there shouldn't be any need for conversion cycles, and so my next ABus > is 0x00000E6C. But apparently the OPB monitor flags this as an error. I > think it expects the ABus to be incremented only by 1, since the > previous xfer_size is byte. I think this is correct _if_ I'm using the > basic dynamic sizing and _not_ the byte-enable architecture. > > Digging into the OPB monitor code, it seems that the process that > checks for this particular scenario only checks for the xfer_sizes and > xfer_acks - there's no references to byte-enable signals. The OPB > monitor version I have is 2.0.1, and it seems to be the latest version > that you can get from Xilinx. > > Any help / input is greatly appreciated. > > Thanks, > > dumak23Hi dumak, Sorry I cannot help you, but I have some questions since you are doing the thing that I want to do by myself. I have about the same problems. I am exploring OPB Master capabilities designed with EDK's Create - Import peripheral wizard. I inserted Chipscope IBA/OPB core to my desing to monitor OPB bus. The problem are the signal names in ChipScope Analyzer - there are 80 of them with NO names attached. How to correctly assign signal names (or should I make a custom core with ChipScope Core Generator)? Cheers, Guru
Reply by ●March 28, 20062006-03-28
On 28 Mar 2006 01:16:39 -0800, "Guru" <ales.gorkic@email.si> wrote:><...>> >Sorry I cannot help you, but I have some questions since you are doing >the thing that I want to do by myself. I have about the same problems. >I am exploring OPB Master capabilities designed with EDK's Create - >Import peripheral wizard. I inserted Chipscope IBA/OPB core to my >desing to monitor OPB bus. The problem are the signal names in >ChipScope Analyzer - there are 80 of them with NO names attached. How >to correctly assign signal names (or should I make a custom core with >ChipScope Core Generator)? >Look at a directory with a name of the sort "implementation\chipscope_opb_iba_0_wrapper", you will sess a .cdc file, this is the file to load from Chipscope analyzer with the signal name assignment. Best luck, Zara
Reply by ●March 28, 20062006-03-28
Reply by ●March 28, 20062006-03-28
Reply by ●March 29, 20062006-03-29
Hi Dumak, Zara was right (thank you :)). I found .cdc file at the "implementation\chipscope_opb_iba_0_wrapper". It helps a lot. Thnx, Guru
Reply by ●March 29, 20062006-03-29