combinatorial always blocks + for-loops in XST

All-

I'm using Spartan 3 + XST 7.1sp4.  In the code below, is there a way to
use a combinatorial always block and a for-loop to make it more
readable and not take 32 lines of source?

-Jeff


wire [31:0] a;
reg [7:0] b [31:0];
reg [2:0] bit;

assign a = {
             b[31][bit],
                :
                :
             b[10][bit],
             b[9][bit],
             b[8][bit],
             b[7][bit],
             b[6][bit],
             b[5][bit],
             b[4][bit],
             b[3][bit],
             b[2][bit],
             b[1][bit],
             b[0][bit]
           };

"Jeff Brower" <jbrower@signalogic.com> wrote in message 
news:1143564063.943670.85530@i40g2000cwc.googlegroups.com...
> All-
>
> I'm using Spartan 3 + XST 7.1sp4.  In the code below, is there a way to
> use a combinatorial always block and a for-loop to make it more
> readable and not take 32 lines of source?
>
> -Jeff

This should work:

integer i;
always @*
  for( i=0; i<32; i=i+1 )
    a[i] = b[i][bit]; 

Thanks John...

XST complains that a is a wire.

-Jeff

Sorry...

reg [31:0] a;
reg [7:0] b [31:0];
reg [2:0] bit;
integer i;
always @*
  for( i=0; i<32; i=i+1 )
    a[i] = b[i][bit];

"Jeff Brower" <jbrower@signalogic.com> wrote in message 
news:1143566575.122908.265400@e56g2000cwe.googlegroups.com...
> Thanks John...
>
> XST complains that a is a wire.
>
> -Jeff
> 

John-

> reg [31:0] a;
> reg [7:0] b [31:0];
> reg [2:0] bit;
> integer i;
> always @*
>   for( i=0; i<32; i=i+1 )
>     a[i] = b[i][bit];

Well... I need a to be a wire.  I guess there may not be a way to take
advantage of for-loops with assign statements.

-Jeff

"Jeff Brower" <jbrower@signalogic.com> wrote in message 
news:1143568299.707740.315120@i39g2000cwa.googlegroups.com...
> John-
>
>> reg [31:0] a;
>> reg [7:0] b [31:0];
>> reg [2:0] bit;
>> integer i;
>> always @*
>>   for( i=0; i<32; i=i+1 )
>>     a[i] = b[i][bit];
>
> Well... I need a to be a wire.  I guess there may not be a way to take
> advantage of for-loops with assign statements.
>
> -Jeff

A doesn't need to be declared a wire to be a combinatorial value.  Because 
the always block is a combinatorial block, the reg value is a combinatorial 
result, not implemented as a flip-flop or "register" primitive.  The always 
constructs need reg-declared variables to work.

Change "a" to reg per above.
Compile.
Realize.
Smile. 

John-

> reg [31:0] a;
> reg [7:0] b [31:0];
> reg [2:0] bit;
> integer i;
> always @*
>   for( i=0; i<32; i=i+1 )
>     a[i] = b[i][bit];

> A doesn't need to be declared a wire to be a combinatorial value.  Because
> the always block is a combinatorial block, the reg value is a combinatorial
> result, not implemented as a flip-flop or "register" primitive.  The always
> constructs need reg-declared variables to work.

Ok, got it.  I suppose I can think of it as a latch, always enabled.
But to let you know XST doesn't like the "*".  To synthesize, I had to
use:

always begin
  for (i=0; i<32; i=i+1)
    a[i] = b[i][bit];
end

Is it equivalent?  XST complains that b and bit are missing from the
sensitivity list.

-Jeff

The "always @*" or "always @(*)" equivalent construct is a Verilog2001 
catchall for the sensitivity list.  If you don't choose Verilog2001 support 
(it's optional in the Synplify compiler) or if XST 7.1.04i doesn't support 
that construct, you would do best to include the full sensitivity list - 
"always @(b or bit)"

Also - since the "for" statement is a single statement, the begin/end 
constructs are superfluous; they do no harm but they add nothing.  It's only 
when there are multiple lines that the begin/end are needed.


"Jeff Brower" <jbrower@signalogic.com> wrote in message 
news:1143571625.151565.45160@v46g2000cwv.googlegroups.com...
> John-
>
>> reg [31:0] a;
>> reg [7:0] b [31:0];
>> reg [2:0] bit;
>> integer i;
>> always @*
>>   for( i=0; i<32; i=i+1 )
>>     a[i] = b[i][bit];
>
>> A doesn't need to be declared a wire to be a combinatorial value. 
>> Because
>> the always block is a combinatorial block, the reg value is a 
>> combinatorial
>> result, not implemented as a flip-flop or "register" primitive.  The 
>> always
>> constructs need reg-declared variables to work.
>
> Ok, got it.  I suppose I can think of it as a latch, always enabled.
> But to let you know XST doesn't like the "*".  To synthesize, I had to
> use:
>
> always begin
>  for (i=0; i<32; i=i+1)
>    a[i] = b[i][bit];
> end
>
> Is it equivalent?  XST complains that b and bit are missing from the
> sensitivity list.
>
> -Jeff
> 

John-

Many thanks.

> The "always @*" or "always @(*)" equivalent construct is a Verilog2001
> catchall for the sensitivity list.  If you don't choose Verilog2001 support
> (it's optional in the Synplify compiler) or if XST 7.1.04i doesn't support
> that construct, you would do best to include the full sensitivity list -
> "always @(b or bit)"

XST burps up "Unexpected event in always block sensitivity list." with
that syntax.

Even going sans list, the result is still not equivalent to the lengthy
assign statement.  XST changes routing enough to add 1 nsec on a local
clock net that I use as my canary.

> Also - since the "for" statement is a single statement, the begin/end
> constructs are superfluous; they do no harm but they add nothing.  It's only
> when there are multiple lines that the begin/end are needed.

Ya know.  Sorry... I've been trying so many darn things I kept 'em
there for experimenting.

-Jeff

"Jeff Brower" <jbrower@signalogic.com> wrote in message 
news:1143583435.146145.259790@v46g2000cwv.googlegroups.com...
> Even going sans list, the result is still not equivalent to the lengthy
> assign statement.  XST changes routing enough to add 1 nsec on a local
> clock net that I use as my canary.

*Never* count on a reference net for timing information to give you a clue 
on synthesis.  Synthesizers will move things around and place & routes 
confuse things further.  Only by checking the technology view post-synthesis 
will the "equivalence" be checked 100% to my satisfaction.