FSL to VHDL interface

Hello,

I'm having great difficulty interfacing my FSL to my external (from
microblaze point of view) VHDL.  I want an FSL to communicate between
Microblaze and my external VHDL.  I want to be able to import the .xmp
file to my ISE project and then create the instantiation template
(wrapper) for the XMP file (*_stub.vhd).  In the file I need to see the
FSL control signals, data etc.  I cannot get this to happen.  I'm
thinking there needs to be some kind of interface VHDL inside of the
EDK project and then make those signals external.  Please offer any
help you can.  I'm frustrated.... at the end of my rope :).

Thanks,
Dale

Hi Dale,

dale.prather@gmail.com wrote:

> I'm having great difficulty interfacing my FSL to my external (from
> microblaze point of view) VHDL.  I want an FSL to communicate between
> Microblaze and my external VHDL.  I want to be able to import the .xmp
> file to my ISE project and then create the instantiation template
> (wrapper) for the XMP file (*_stub.vhd).  In the file I need to see the
> FSL control signals, data etc.  I cannot get this to happen.  I'm
> thinking there needs to be some kind of interface VHDL inside of the
> EDK project and then make those signals external.  Please offer any
> help you can.  I'm frustrated.... at the end of my rope :).

You'll probably need to create explicit FSL signals and bring these out
as toplevel ports in the EDK / MicroBlaze design.

And at the top of the MHS file, you'll have typical port declarations

PORT FSL0_S_CLK = fsl0_s_clk, DIR = O
PORT FSL0_S_DATA = fsl0_s_data, DIR = I
PORT FSL0_S_CONTROL = fsl0_s_control, DIR = I
PORT FSL0_S_EXISTS = fsl0_s_exists, DIR = I
PORT FSL0_S_READ = fsl0_s_read, DIR =O

then later


begin microblaze
...
  PARAMETER C_FSL_LINKS=1
...
  PORT FSL0_S_CLK = fsl0_s_clk
  PORT FSL0_S_DATA = fsl0_s_data
  PORT FSL0_S_CONTROL = fsl0_s_control
  PORT FSL0_S_EXISTS = fsl0_s_exists
  PORT FSL0_S_READ = fsl0_s_read
...
end

This is for a microblaze slave (incoming) port, it will be a little
different for outgoing ports, but the idea should be the same.

Does that hlep
?

John

John,
Thanks.  This does help a lot.  I appreciate your post.  I'm still
slightly confused about this master and slave terminology.  Myself and
a couple others have been trying to understand it, but it's pretty
convoluted.  Is master always an output from microblaze and slave
always an input to microblaze?

Also, I'm a little confused as to why when I add an FSL to microblaze,
I get a SFSL and a MFSL.  This implies that the FSL is bidirectional
when it's stated in the FSL datasheet that it's a unidirectional bus.
Confusing.  I wish they would've used terms other than master and
slave.

I'm assuming the port map you provided above is from the viewpoint of
ublaze?  The FLS0_S_READ and FLS0_S_CLK signals are outputs.  My
question is, outputs to where?  I don't know why they'd go to the VHDL.
 They should go to the FSL, as they are the control signals that pop
off the data into ublaze.

I'm guessing you're in Austrailia?  If that's true you're sleeping and
I hope to here from you tomorrow.

Regards,
Dale

Dale,

Take a look at the section Fast Simplex Link Interface Description of
the mb_ref guide (page 50 in the 7.1 version).

And the datasheet DS449 that describes FSL in more detiail.

The following MHS fragment might help clear things up a bit.

Regards,

John


# MicroBlaze subsystem ports

PORT fsl_incoming_m_clk = fsl_incoming_m_clk, DIR = I
PORT fsl_incoming_m_data = fsl_incoming_m_data, DIR = I, VEC=[0:31]
PORT fsl_incoming_m_control = fsl_incoming_m_control, DIR = I
PORT fsl_incoming_m_write = fsl_incoming_m_write, DIR = I
PORT fsl_incoming_m_full = fsl_incoming_m_full, DIR = O

PORT fsl_outgoing_s_clk = fsl_outgoing_s_clk, DIR = I
PORT fsl_outgoing_s_data = fsl_outgoing_s_data, DIR = O, VEC=[0:31]
PORT fsl_outgoing_s_control = fsl_outgoing_s_control, DIR = o
PORT fsl_outgoing_s_read = fsl_outgoing_s_read, DIR = I
PORT fsl_outgoing_s_exists = fsl_outgoing_s_exists, DIR = O


begin microblaze
...
  PARAMETER C_FSL_PORTS= 1
...
  BUS_INTERFACE SFSL0 = my_fsl_incoming
  BUS_INTERFACE MFSL0 = my_fsl_outgoing
...
end

# Incoming FSL channel - data from VHDL to microblaze
# Slave port connects to MicroBlaze
# Master port wired to toplevel ports

begin fsl
 PARAMETER INSTANCE=my_fsl_incoming
 PARAMETER HW_VER = 2.00.a
 PORT SYS_Rst sys_rst
 PORT FSL_CLK = sys_clk

 PORT FSL_M_Clk = fsl_incmoing_m_clk
 PORT FSL_M_Data = fsl_incoming_m_data
 PORT FSL_M_Control = fsl_incoming_m_control
 PORT FSL_M_Write = fsl_incoming_m_write
 PORT FSL_M_Full = fsl_incoming_m_full
end

# Outgoing FSL channel - data from microblaze to VHDL
# Master port connects to MicroBlaze
# Slave port wired to toplevel ports
begin fsl
 PARAMETER INSTANCE=my_fsl_outgoing
 PARAMTER HW_VER = 2.00.a
 PORT SYS_Rst sys_rst
 PORT FSL_CLK = sys_clk

 PORT FSL_S_Clk = fsl_outgoing_s_clk
 PORT FSL_S_Data = fsl_outgoing_s_data
 PORT FSL_S_Control = fsl_outgoing_s_control
 PORT FSL_S_Read = fsl_outgoing_s_read
 PORT FSL_S_Exists = fsl_outgoing_s_exists
end


dale.prather@gmail.com wrote:
> John,
> Thanks.  This does help a lot.  I appreciate your post.  I'm still
> slightly confused about this master and slave terminology.  Myself and
> a couple others have been trying to understand it, but it's pretty
> convoluted.  Is master always an output from microblaze and slave
> always an input to microblaze?
> 
> Also, I'm a little confused as to why when I add an FSL to microblaze,
> I get a SFSL and a MFSL.  This implies that the FSL is bidirectional
> when it's stated in the FSL datasheet that it's a unidirectional bus.
> Confusing.  I wish they would've used terms other than master and
> slave.
> 
> I'm assuming the port map you provided above is from the viewpoint of
> ublaze?  The FLS0_S_READ and FLS0_S_CLK signals are outputs.  My
> question is, outputs to where?  I don't know why they'd go to the VHDL.
>  They should go to the FSL, as they are the control signals that pop
> off the data into ublaze.
> 
> I'm guessing you're in Austrailia?  If that's true you're sleeping and
> I hope to here from you tomorrow.
> 
> Regards,
> Dale
> 

John,
Thank you for your input.  It has helped tremendously.

Hopefully, just one more question.  When I do this:

  BUS_INTERFACE SFSL0 = my_fsl_incoming
  BUS_INTERFACE MFSL0 = my_fsl_outgoing

I get these two errors, which I think is at the root of the confusion.


ERROR:MDT - fsl_v20 (my_fsl_incoming) -
   C:\Xil_Proj\Bal_Con\Current_Sense\PWM2\system.mhs line 197 - must
have
   atleast 1 master assigned!

ERROR:MDT - fsl_v20 (my_fsl_outgoing) -
   C:\Xil_Proj\Bal_Con\Current_Sense\PWM2\system.mhs line 210 - must
have
   atleast 1 slave assigned!

For now, to fix it, I've done this:

 BUS_INTERFACE MFSL0 = my_fsl_incoming
 BUS_INTERFACE SFSL0 = my_fsl_incoming
 BUS_INTERFACE SFSL1 = my_fsl_outgoing
 BUS_INTERFACE MFSL1 = my_fsl_outgoing

Any comments on the errors or my solution?

Thanks,
Dale

dale.prather@gmail.com wrote:
> John,
> Thank you for your input.  It has helped tremendously.
> 
> Hopefully, just one more question.  When I do this:
> 
>   BUS_INTERFACE SFSL0 = my_fsl_incoming
>   BUS_INTERFACE MFSL0 = my_fsl_outgoing
> 
> I get these two errors, which I think is at the root of the confusion.
> 
> 
> ERROR:MDT - fsl_v20 (my_fsl_incoming) -
>    C:\Xil_Proj\Bal_Con\Current_Sense\PWM2\system.mhs line 197 - must
> have
>    atleast 1 master assigned!
> 
> ERROR:MDT - fsl_v20 (my_fsl_outgoing) -
>    C:\Xil_Proj\Bal_Con\Current_Sense\PWM2\system.mhs line 210 - must
> have
>    atleast 1 slave assigned!
> 
> For now, to fix it, I've done this:
> 
>  BUS_INTERFACE MFSL0 = my_fsl_incoming
>  BUS_INTERFACE SFSL0 = my_fsl_incoming
>  BUS_INTERFACE SFSL1 = my_fsl_outgoing
>  BUS_INTERFACE MFSL1 = my_fsl_outgoing
> 
> Any comments on the errors or my solution?
> 
> Thanks,
> Dale
> 

Hi,

In your fix you have connect two outgoing FSL ports on MicroBlaze to two 
incoming FSL ports. So this MicroBlaze can send data to itself.
Not sure if this is what you want to do.

Since you want to connect to the outside world of EDK, the tools doesn't 
see a Master-Slave pair in your first attempt. It's the DRC of the tools 
that errors out.

You can't use the BUS_INTERFACE for connect since their is no 
slave/master BUS_INTERFACE for them.
You must connect each signal individual as John proposed in his first reply.

G�ran

If I don't use BUS_INTERFACE it says my FSL is not connected to
anything.  Here is my MHS file.  Does anyone have an idea how to make
it work, or at least what's wrong with it?  At this point, I'm just
trying to get a single slave FSL working.  To me that means an FSL
which inputs data into microblaze from my ISE project (VHDL).



PARAMETER VERSION = 2.1.0


 PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out,
VEC = [0:7], DIR = O
 PORT fpga_0_Push_Buttons_3Bit_GPIO_in_pin =
fpga_0_Push_Buttons_3Bit_GPIO_in, VEC = [0:0], DIR = I
 PORT fpga_0_DIP_Switches_8Bit_GPIO_in_pin =
fpga_0_DIP_Switches_8Bit_GPIO_in, VEC = [0:7], DIR = I
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK
 PORT sys_rst_pin = sys_rst_s, DIR = I
 PORT ext_interrupt = ext_interrupt, DIR = I, SIGIS = Interrupt,
SENSITIVITY = EDGE_RISING
 PORT FSL0_M_Clk = FSL0_M_Clk, DIR = I
 PORT FSL0_M_Data = FSL0_M_Data, DIR = I, VEC = [0:31]
 PORT FSL0_M_Write = FSL0_M_Write, DIR = I
 PORT FSL0_M_Full = FSL0_M_Full, DIR = O
 PORT FSL0_S_CLK = fsl0_s_clk, DIR = O
 PORT FSL0_S_DATA = fsl0_s_data, DIR = I, VEC = [0:31]
 PORT FSL0_S_EXISTS = fsl0_s_exists, DIR = I
 PORT FSL0_S_READ = fsl0_s_read, DIR =O

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 0
 PARAMETER C_NUMBER_OF_PC_BRK = 0
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
 PARAMETER C_INTERRUPT_IS_EDGE = 1
 PARAMETER C_EDGE_IS_POSITIVE = 1
 PARAMETER C_FSL_LINKS = 1
 PARAMETER C_USE_MSR_INSTR = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT CLK = sys_clk_s
 PORT FSL0_S_CLK = fsl0_s_clk
 PORT FSL0_S_DATA = fsl0_s_data
 PORT FSL0_S_EXISTS = fsl0_s_exists
 PORT FSL0_S_READ = fsl0_s_read
 PORT Interrupt = ext_interrupt
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEMSIZE = 16384
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END

BEGIN opb_gpio
 PARAMETER INSTANCE = Push_Buttons_3Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 1
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 PARAMETER C_INTERRUPT_PRESENT = 1
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_in = fpga_0_Push_Buttons_3Bit_GPIO_in
 PORT IP2INTC_Irpt = Push_Buttons_3Bit_IP2INTC_Irpt
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 20.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN fsl_v20
 PARAMETER INSTANCE = my_fsl_incoming
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_USE_CONTROL = 0
 PORT SYS_Rst = sys_rst_s
 PORT FSL_CLK = dcm_clk_s
 PORT FSL_S_CLK = fsl0_s_clk
 PORT FSL_S_DATA = fsl0_s_data
 PORT FSL_S_EXISTS = fsl0_s_exists
 PORT FSL_S_READ = fsl0_s_read
 PORT FSL_M_Clk = FSL0_M_Clk
 PORT FSL_M_Data = FSL0_M_Data
 PORT FSL_M_Write = FSL0_M_Write
 PORT FSL_M_Full = FSL0_M_Full
END

Hi,

You're right. I never connected to outside world with the FSL bus 
defined internally. I connect MicroBlaze signals directly to outside.
I will inform the team about this.

In this case, I would solve this by creating a dummy peripheral which 
just tunnels the FSL signals through to the outside world.

The .mpd file would look like something like this:

BEGIN FSL_TUNNEL_TO_OUTSIDE
OPTION IPTYPE=PERIPHERAL
OPTION IMP_NETLIST=TRUE

# Define bus interface
BUS_INTERFACE BUS=MFSL, BUS_STD=FSL, BUS_TYPE=UNDEF
BUS_INTERFACE BUS=SFSL, BUS_STD=FSL, BUS_TYPE=UNDEF

# FSL slave port
PORT FSL_S_CLK     = FSL_S_Clk,     DIR=in, BUS=SFSL
PORT FSL_S_READ    = FSL_S_Read,    DIR=in, BUS=SFSL
PORT FSL_S_DATA    = FSL_S_Data,    DIR=out, VEC=[0:31], BUS=SFSL
PORT FSL_S_CONTROL = FSL_S_Control, DIR=out, BUS=SFSL
PORT FSL_S_EXISTS  = FSL_S_Exists,  DIR=out, BUS=SFSL

# FSL master port
PORT FSL_M_CLK     = FSL_M_Clk,     DIR = out,  BUS = MFSL
PORT FSL_M_WRITE   = FSL_M_Write,   DIR = out, BUS = MFSL
PORT FSL_M_DATA    = FSL_M_Data,    DIR = out, VEC = [0:31], BUS = MFSL
PORT FSL_M_CONTROL = FSL_M_Control, DIR = out, BUS = MFSL
PORT FSL_M_FULL    = FSL_M_Full,    DIR = in, BUS = MFSL

# FSL master signals coming in from outside
PORT EXT_FSL_M_CLK     = "", DIR=in
PORT EXT_FSL_M_WRITE   = "", DIR=in
PORT EXT_FSL_M_DATA    = "", DIR=out
PORT EXT_FSL_M_CONTROL = "", DIR=out
PORT EXT_FSL_M_FULL    = "", DIR=out

# FSL slave signals going out to the outside
PORT EXT_FSL_S_CLK     = "", DIR=out
PORT EXT_FSL_S_READ    = "", DIR=out
PORT EXT_FSL_S_DATA    = "", DIR=in
PORT EXT_FSL_S_CONTROL = "", DIR=in
PORT EXT_FSL_S_EXISTS  = "", DIR=in

END


The VHDL code will look like this:

library ieee;
use ieee.std_logic_1164.all;

entity fsl_tunnel_to_outside is
   port (
     -- FSL master signals
     FSL_M_Clk     : out std_logic;
     FSL_M_Data    : out std_logic_vector(0 to 31);
     FSL_M_Control : out std_logic;
     FSL_M_Write   : out std_logic;
     FSL_M_Full    : in  std_logic;

     -- FSL slave signals
     FSL_S_Clk     : in  std_logic;
     FSL_S_Data    : in  std_logic_vector(0 to 31);
     FSL_S_Control : in  std_logic;
     FSL_S_Read    : in  std_logic;
     FSL_S_Exists  : out std_logic;

     -- FSL master signals coming in from outside
     EXT_FSL_M_CLK     : in  std_logic;
     EXT_FSL_M_WRITE   : in  std_logic;
     EXT_FSL_M_DATA    : in  std_logic_vector(0 to 31);
     EXT_FSL_M_CONTROL : in  std_logic;
     EXT_FSL_M_FULL    : out std_logic;

     -- FSL slave signals going out to the outside
     EXT_FSL_S_CLK     : out std_logic;
     EXT_FSL_S_READ    : out std_logic;
     EXT_FSL_S_DATA    : out std_logic_vector(0 to 31);
     EXT_FSL_S_CONTROL : out std_logic;
     EXT_FSL_S_EXISTS  : in  std_logic
     );
end entity fsl_tunnel_to_outside;

architecture IMP of fsl_tunnel_to_outside is

begin  -- architecture IMP

   FSL_M_Clk      <= EXT_FSL_M_CLK;
   FSL_M_Data     <= EXT_FSL_M_DATA;
   FSL_M_Control  <= EXT_FSL_M_CONTROL;
   FSL_M_Write    <= EXT_FSL_M_WRITE;
   EXT_FSL_M_FULL <= FSL_M_FULL;

   EXT_FSL_S_CLK     <= FSL_S_Clk;
   EXT_FSL_S_CONTROL <= FSL_S_Control;
   EXT_FSL_S_DATA    <= FSL_S_Data;
   EXT_FSL_S_READ    <= FSL_S_Read;
   FSL_S_Exists      <= EXT_FSL_S_EXISTS;

end architecture IMP;


In the system.mhs you can do this now if you want a both incoming and 
outgoing FSL bus


BEGIN fsl_v20
  PARAMETER INSTANCE = my_fsl_incoming
  PARAMETER HW_VER = 2.00.a
  PARAMETER C_USE_CONTROL = 0
  PORT SYS_Rst = sys_rst_s
  PORT FSL_CLK = dcm_clk_s
END

BEGIN fsl_v20
  PARAMETER INSTANCE = my_fsl_outgoing
  PARAMETER HW_VER = 2.00.a
  PARAMETER C_USE_CONTROL = 0
  PORT SYS_Rst = sys_rst_s
  PORT FSL_CLK = dcm_clk_s
END

BEGIN fsl_tunnel_to_outside
  PARAMETER INSTANCE = fsl_tunnel_to_outside_0
  PARAMETER HW_VER = 1.00.a
  BUS_INTERFACE MFSL = my_fsl_incoming
  BUS_INTERFACE SFSL = my_fsl_outgoing

  PORT EXT_FSL_M_Clk = EXT_FSL0_M_Clk
  PORT EXT_FSL_M_Data = EXT_FSL0_M_Data
  PORT EXT_FSL_M_Write = EXT_FSL0_M_Write
  PORT EXT_FSL_M_Control = EXT_FSL0_M_Control
  PORT EXT_FSL_M_Full = EXT_FSL0_M_Full

  PORT EXT_FSL_S_Clk = EXT_FSL0_S_Clk
  PORT EXT_FSL_S_Data = EXT_FSL0_S_Data
  PORT EXT_FSL_S_Read = EXT_FSL0_S_Read
  PORT EXT_FSL_S_Control = EXT_FSL0_S_Control
  PORT EXT_FSL_S_Exists = EXT_FSL0_S_Exists

I want to thank both of you for helping me understand this.  I think I
finally have my brain wrapped around this twisted stuff, thanks to you.
 I'm on my way to getting it to work.  I was hoping to find a way
around this tunnel method.  That's not going to happen, but in trying
to do so, I have a much better understanding of how FSLs, EDK, MHSs,
MPDs and the associated syntaxes work.

Thanks,
Dale

For anyone facing the same problem, here is a nice document to clear up
a little of the confusion.  The file psf_rm.pdf which describes MPD,
MHS, MSS etc....  syntax and usage guide can be found in this
directory:   %XILINX_EDK%\doc directory.