PCB Bypass Caps

Hi

I need to layout a Virtex 2 Pro board using a 672 BGA package. Does anyone
have any tips for the placement of the bypass caps. I want to use 0603 caps
and normal PTH vias. I can see that it might get a bit crowded trying to
position a lot of caps under the device near to the power pins with all
those vias.

Cheers

Jon

A good development board (Avnet, Insight, Xilinx) to look at, can give 
you some ideas.
Aurash

maxascent wrote:
> Hi
> 
> I need to layout a Virtex 2 Pro board using a 672 BGA package. Does anyone
> have any tips for the placement of the bypass caps. I want to use 0603 caps
> and normal PTH vias. I can see that it might get a bit crowded trying to
> position a lot of caps under the device near to the power pins with all
> those vias.
> 
> Cheers
> 
> Jon

Also look at the Virtex II (not pro) User's guide.  Chapter 5 shows
good layout
practices and routability guidelines.  Among other things note that the
via
pattern for the fully populated grid parts creates a "+" shaped opening
that
can be used to place your bypass caps.

Aurelian Lazarut wrote:
> A good development board (Avnet, Insight, Xilinx) to look at, can give
> you some ideas.
> Aurash
>
> maxascent wrote:
> > Hi
> >
> > I need to layout a Virtex 2 Pro board using a 672 BGA package. Does anyone
> > have any tips for the placement of the bypass caps. I want to use 0603 caps
> > and normal PTH vias. I can see that it might get a bit crowded trying to
> > position a lot of caps under the device near to the power pins with all
> > those vias.
> > 
> > Cheers
> > 
> > Jon

maxascent wrote:
> Hi
>
> I need to layout a Virtex 2 Pro board using a 672 BGA package. Does anyone
> have any tips for the placement of the bypass caps. I want to use 0603 caps
> and normal PTH vias. I can see that it might get a bit crowded trying to
> position a lot of caps under the device near to the power pins with all
> those vias.

The main principal behind decoupling caps is to minimize the area of
the loop made by path from the power pin through the trace, cap and
trace back to a ground pin.  This area determines the inductance of the
loop and limits the effectiveness of the capacitors.  Anything that
enlarges the loop area will create a problem with high speed
decoupling.

My recommendation is to use even smaller caps, 0402 is good, and to put
them right at the Vcc pins on the other side of the board, of course.
If you check the impedance curves for ceramic chip caps you will find
that at the frequencies of interest, they are inductive.  So the
actuall value of capacitace is not so important.  The smaller package
normally has lower inductance and therefore has a lower impedance
regardless of capacitance.  I checked these graphs a few years ago when
0402 was not so common and found that a 0.01 uF 0603 cap had a lower
impedance than an 0805 0.1 uF cap.

So focus on lowering the impedance at the important frequencies, not
necessarily on adding capacitance.

There are low inductance 0306 and 0508 capacitor packages that have the
terminations on the broad sides rather than the narrow ends.  Also
putting the capacitor's power and ground vias beside the cap, as close
to each other (and the cap) as possible helps cancel effective
inductance (minimize loop area), especially compared to vias off each
end of the cap. Using a pair of vias on both sides helps even more.
Capacitors on the same side of the board should not share vias, but
capacitors on opposite sides should (current flow directions cancel).

Andy

Andy wrote:
> There are low inductance 0306 and 0508 capacitor packages that have the
> terminations on the broad sides rather than the narrow ends.  Also
> putting the capacitor's power and ground vias beside the cap, as close
> to each other (and the cap) as possible helps cancel effective
> inductance (minimize loop area), especially compared to vias off each
> end of the cap. Using a pair of vias on both sides helps even more.
> Capacitors on the same side of the board should not share vias, but
> capacitors on opposite sides should (current flow directions cancel).
>
> Andy

I'd say 0306 won't buy much in comparison to 0603 as the bonding
wire lengths will be defining the loop inductance in both cases.
  At 1.27 mm pitched BGAs, I drill all pads and put the decouplng
capacitors right on the bottom side pads (where power and GND
are typically next to one another).
 The decoupling at higher speeds is done by
the (power to GND) plane to plane capacitance, and of course
by the on chip decoupling which must have been taken
care of by the manucfacturer.

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

"maxascent" <maxascent@yahoo.co.uk> wrote in message 
news:T9CdncycrbbpP7bZRVn_vA@giganews.com...
> Hi
>
> I need to layout a Virtex 2 Pro board using a 672 BGA package. Does anyone
> have any tips for the placement of the bypass caps. I want to use 0603 
> caps
> and normal PTH vias. I can see that it might get a bit crowded trying to
> position a lot of caps under the device near to the power pins with all
> those vias.
>
> Cheers
>
> Jon

Jon -

The best thing you can do for yourself is to use solid power and ground 
planes in your board and place them as close together as possible. A 
dielectric thickness between PCB layers of 0.004" (4 mils) is mainstream 
these days. As rickman stated, the goal is to minimize the loop 
area/inductance between the BGA balls and the bypass cap. Keeping the places 
close together is far more important in achieving this than placing the caps 
close to the balls, which is often impossible. There is a wealth of 
literature available on this subject if you look around for it.

Next, place the bypass caps for each voltage rail on the side of the board 
that is closest to the power/GND plane pair in your PCB stackup. Think loop 
area again. The vias from the cap to the planes form a loop, so the shorter 
the distance the better.

Third, there are good and bad ways to mount bypass caps. Andy mentioned 
this. Xilinx shows the good and bad mounting methods in XAPP623. I highly 
recommend you read this app note. Going back to loop area, keeping the two 
vias from the cap to the planes close together lowers the loop area. Using 
multiple vias lowers is even more, but I don't recommend this because it 
clogs routing and pokes even more holes in your already Swiss-cheesed power 
and ground planes.

Lastly, place the caps as close to the package as you can without destroying 
your routing channels. If you do everything above correctly then the 
distance from the BGA balls to the bypass caps is not that critical. Within 
a couple of inches is fine.

If you research this topic you'll also see varying recommendations on how to 
achieve a flat PDS (power distribution system) impedance over as wide a 
frequency range as possible by using several different cap values. This 
complicates the process a little but research shows it actually works. I 
still get away with using 0.01uF 0402 caps as my general bypass, with a few 
larger value (e.g., 2.2uF or 4.7uF) scattered around. Typically one larger 
value be I/O bank, one for VCCAUX, and maybe a couple for VCCINT.

Good luck!

Rob 

Hi

Thanks all for the great advice. Now just one more question :). Would I be
ok to use a power plane with multiple islands for the different voltages.

Cheers

Jon

maxascent wrote:
> Hi
>
> Thanks all for the great advice. Now just one more question :). Would I be
> ok to use a power plane with multiple islands for the different voltages.

Sort of like the first question, you can get a lot of different answers
and they will all be correct.  I find splitting planes is ok.  But it
is not easy to do well.  The resistance of a sheet like a PCB plane can
be expressed as "squares".  For a given material and thickness, there
will be a given amount of resistance per square area.  It does not
matter what the overall shape is, it can be broken into squares of any
size and each one will have the same resistance.  I've been told that a
typical PCB will have about 1 mOhm per square.  So don't make your
power planes sections too long and narrow or the resistance will start
to be significant.

In general, the power and ground plane coupling provides capacitance at
the highest frequencies where caps are too high impedance to do much
good.  So don't skimp on the planes, keep them as large as possible.
In the end you may need to add a second power layer or mix power and
signals just because most parts require two voltages and running split
power planes to the same part can be difficult.

rickman wrote:
> In general, the power and ground plane coupling provides capacitance at
> the highest frequencies where caps are too high impedance to do much
> good.  So don't skimp on the planes, keep them as large as possible.
> In the end you may need to add a second power layer or mix power and
> signals just because most parts require two voltages and running split
> power planes to the same part can be difficult.

Another right answer  :-)

But consider:  while the capacitance is larger to have 100 sqare inches 
rather than 16, the point where the open edges of the PCB make the plane 
capacitance worthless due to replections (think quarter wave antenna 
here) is 2.5x worse.  The bulk capacitance is better but the board 
capacitance will "open circuit" at a lower frequency.

As Howard Johnson pointed out in last week's Xilinx webcast, that point 
is rather moot for modern BGAs with the chips separated from the board 
by the "masking inductance" to where those higher frequencies are a 
problem for the BGA package or the chip itself.

Small power islands can be good as long as they have the appropriate 
decoupling to augment the power supply's response.  Closer power/ground 
spacing means better capacitance - there are esoteric products that 
reduce the spacing to the 2 mil and under range but I don't know of any 
PCB houses that use it.  Smaller planes are actually better if you have 
high frequency/current devices that have minimal impedance to the board 
when mounted where that "masking inductance" isn't an issue and the size 
of the board dictates where the distributed capacitance becomes less 
effective.  Luckily we don't have many situations where that's a worry.

Resistance to the island is a concern.  Capacitance on that island is a 
concern.  One of the larger problems is when designers reference signals 
to those power islands and cross from island-to-island without 
significant decoupling island-to-island resulting in horrific crosstalk. 
   If you want to reference signals to split planes, make sure they have 
a return current path that can *also* jump the plane split.